Oldest | Popular
Spencer vs Stallman (0 replies, 01/01/70)
V System (0 replies, 01/01/70)
Code Density (0 replies, 01/01/70)
Unix with dynamic loading (0 replies, 01/01/70)
Shared Libraries et all. See also Multics. (0 replies, 01/01/70)
net.arch is being renamed comp.arch (0 replies, 11/07/86)
Information Request : G-64/G-96 Bus (0 replies, 11/08/86)
Neurotic Nomenclature (0 replies, 11/11/86)
Why optical disks are slow to seek etc... (1 reply, 11/11/86)
Floating point accuracy (3 replies, 11/11/86)
Let's start a trend! (0 replies, 11/12/86)
Speed is the one true performanc (1 reply, 11/13/86)
Floating point conversions... (0 replies, 11/13/86)
an idea for higher capacity disks (2 replies, 11/14/86)
brk's zero-fill behavior on VAXen (0 replies, 11/15/86)
Bit addressibility (0 replies, 11/15/86)
Reliabilty of Crays (0 replies, 11/15/86)
I/O benchmarks (1 reply, 11/18/86)
Why optical disks are slow to seek; an idea for higher capacity disks (2 replies, 11/18/86)
Horror Stories (0 replies, 11/18/86)
>32-bit microprocessors in the works, anyone? (4 replies, 11/20/86)
Undetectable hardware errors (0 replies, 11/20/86)
Please be careful in quoting!! (0 replies, 11/21/86)
Brain-damaged Terminal Contest (0 replies, 11/21/86)
Code prefetch (0 replies, 11/21/86)
Broken computers giving wrong answers (0 replies, 11/22/86)
sizeof (6 replies, 11/24/86)
Speed is the one true performance metric (9 replies, 11/25/86)
Information on Synapse Systems? (1 reply, 11/27/86)
segments and Unix (2 replies, 11/29/86)
Byte size (0 replies, 12/05/86)
Supercomputing Video Course (0 replies, 12/06/86)
Connection Machine Argument (7 replies, 12/07/86)
MACH literature (5 replies, 12/07/86)
MACH literature summary (0 replies, 12/08/86)
How does compiled code use the floating point unit? (7 replies, 12/11/86)
computer devices (1 reply, 12/12/86)
CALL FOR PAPERS: ICS-SUPERCOMPUTING (0 replies, 12/12/86)
four and twenty blackbirds (0 replies, 12/13/86)
Will the Karp Problem Be Solved? (5 replies, 12/13/86)
Dynamic Ram Controller Chip (2 replies, 12/14/86)
How do you say "byte" in French? (19 replies, 12/15/86)
Size of a Byte (0 replies, 12/16/86)
How does compiled code use the floa (5 replies, 12/18/86)
Byte Order: On Holy Wars and a Plea for Peace (11 replies, 12/18/86)
Hardware random number generators are in gambling machines (0 replies, 12/21/86)
random number generator in hardware (13 replies, 12/21/86)
what's a word (2 replies, 12/22/86)
Architecture upgrade (5 replies, 12/30/86)
Call for Papers: ASPLOS-II (0 replies, 01/01/87)
Yearly survey (0 replies, 01/06/87)
detailed description of the current Connection Machine implementation (4 replies, 01/06/87)
Whetstone results for VAXes (0 replies, 01/09/87)
Cost of Designing a New Computer (10 replies, 01/17/87)
Forming Transputer Mailing List (0 replies, 01/18/87)
caches and the kernel (2 replies, 01/19/87)
Parallel Architectures Question... Transputers. (0 replies, 01/20/87)
NEC V60 Microprocessor (0 replies, 01/21/87)
Unix kernel locality of reference (3 replies, 01/22/87)
byte order and positional number systems (1 reply, 01/22/87)
byte order: be reasonable - do it my way... (20 replies, 01/23/87)
Supercomputing Course Offering-Update (0 replies, 01/23/87)
68008 stuff (1 reply, 01/24/87)
varargs (0 replies, 01/26/87)
Call for Papers --- ASPLOS-II (0 replies, 01/27/87)
Optical Disk Videoconference (0 replies, 01/27/87)
PDP-11 compatibility mode in Vaxen (2 replies, 01/28/87)
Available no. of registers (17 replies, 01/29/87)
IEEE Videodisk Video Conference Dates (0 replies, 01/29/87)
Info. about Encore and Sequent (0 replies, 01/30/87)
Weitek 8000/8032/8064 (0 replies, 01/31/87)
Bit operations on 68K (4 replies, 01/31/87)
compatibility mode in DG Eclipses (0 replies, 01/31/87)
BSET on 68020 (0 replies, 02/01/87)
inference from newpaper ads (0 replies, 02/05/87)
Quick way to determine 680{00,10} from 68020 (0 replies, 02/06/87)
compatibility mode in DG Eclips (0 replies, 02/07/87)
Aliasing, etc. in C (11 replies, 02/08/87)
Comet 32 (0 replies, 02/08/87)
Encore vs Sequent -- summary of responses. Thanks a lot ! (0 replies, 02/10/87)
CALL FOR PAPERS - PARALLEL PROCESSING FOR CAD APPLICATIONS (0 replies, 02/10/87)
Graphics Architectures (0 replies, 02/11/87)
Success of IEEE Floating Point Standard (5 replies, 02/11/87)
I've Got The Microprocessor Blues (4 replies, 02/12/87)
NBSLIB formerly Re: Dhrystone Results and Source (0 replies, 02/12/87)
organic microchips (0 replies, 02/13/87)
Success of IEEE 754 (0 replies, 02/14/87)
Thanks for your help on Transputers. (0 replies, 02/14/87)
Article on Next Inc. (0 replies, 02/16/87)
A great magazine for new and old micro technology (0 replies, 02/17/87)
HELP! (0 replies, 02/17/87)
"Dhrystone" REFERENCE WRONG! (0 replies, 02/18/87)
Where did the name "Dhrystone" come from? (6 replies, 02/18/87)
Snell Trees (0 replies, 02/18/87)
registers (0 replies, 02/18/87)
MIPS to offer COBOL (11 replies, 02/18/87)
Where did the name "Dhrystone" (0 replies, 02/18/87)
V-kernel and Unix (0 replies, 02/19/87)
Stack Growth Direction (2 replies, 02/19/87)
SUPERCOMPUTING CALL FOR PAPERS (0 replies, 02/20/87)
GNU C compiler (0 replies, 02/20/87)
01/31/87 Dhrystone Results and Sour (1 reply, 02/23/87)
Abusing pointers (2 replies, 02/24/87)
Anecdote about dereferencing null pointers (1 reply, 02/24/87)
Hypercubes and second note: (6 replies, 02/24/87)
shared memory multiproc. question (12 replies, 02/25/87)
A bit more on Hypercubes (0 replies, 02/26/87)
Why we can't cater to bad code (1 reply, 02/26/87)
Dhrystone benchmark results from GNU C compiler (1 reply, 02/26/87)
RISC Bibliography (0 replies, 02/26/87)
RISC register windows (4 replies, 02/26/87)
HELP!!! I need references for the HEP. (2 replies, 02/26/87)
subroutine frequency (24 replies, 02/26/87)
Setjmp/longjmp and registers (0 replies, 02/27/87)
paging performance (1 reply, 02/28/87)
RISC refer format bibliography (0 replies, 02/28/87)
refer macro package (0 replies, 02/28/87)
Weitek 3332 Question (0 replies, 03/01/87)
Dhrystone and Dhampstone (1 reply, 03/01/87)
01/31/87 Dhrystone Results and Source (20 replies, 03/01/87)
Bad Code (1 reply, 03/02/87)
Discovery of tidbit (0 replies, 03/03/87)
Looking for TI TMS5501 or replacement (0 replies, 03/03/87)
Looking for info on symbolic microcode debugging (0 replies, 03/04/87)
Will caches ever become obsolete? (8 replies, 03/05/87)
Procedure Call Statistics (0 replies, 03/05/87)
regs, aliasing, caller/callee save etc. (0 replies, 03/05/87)
Mythical Man-Month (0 replies, 03/05/87)
Even Bigger RISC Bibliography (0 replies, 03/05/87)
More on register machines (0 replies, 03/06/87)
Brooks (1 reply, 03/06/87)
Definition of Benchmark (0 replies, 03/06/87)
Tightly-coupled, multi-processor UNIX systems? (2 replies, 03/09/87)
Wanted: info on Concurrent supercomputer running LISP (0 replies, 03/09/87)
Optimizing compiler's view on: no. of regs, aliasing, caller/callee save etc. (5 replies, 03/09/87)
Architect's Trap (5 replies, 03/10/87)
PLAIP (0 replies, 03/10/87)
register window machine questions (15 replies, 03/10/87)
This would be funny if it weren't real... (0 replies, 03/10/87)
catering to bad code (28 replies, 03/13/87)
Optimizing compiler's view on: (0 replies, 03/13/87)
Hypercube partitioning - Wrong question (0 replies, 03/14/87)
Tightly-coupled, multi-processor UN (1 reply, 03/14/87)
Memory Management on microcomputers (2 replies, 03/15/87)
Hypercube (5 replies, 03/15/87)
03/15/87 Dhrystone Benchmark Results (1 reply, 03/15/87)
register saving on context switch (9 replies, 03/16/87)
Am29000 announcement; NOT MEANT TO BE ADVERTISEMENT (0 replies, 03/16/87)
Alliant FX/8 parallel benchmarking (0 replies, 03/17/87)
HP Precision Architecture (0 replies, 03/17/87)
AMD's new 32-bit microprocessor (0 replies, 03/17/87)
Van Voorhis sorting network lower bound (0 replies, 03/17/87)
uP Figure of Merit (0 replies, 03/18/87)
IEEE standard IBM PC ? (1 reply, 03/19/87)
path to ELXSI (1 reply, 03/19/87)
Am29000 & register windows (2 replies, 03/21/87)
The serial bottleneck (0 replies, 03/23/87)
68030 Performance (0 replies, 03/23/87)
Josephson Junction computers (12 replies, 03/23/87)
Am29000 and MIPS (11 replies, 03/23/87)
big memories, who needs >~1G (4 replies, 03/25/87)
Entertaining quote on division approximation techniques (0 replies, 03/25/87)
disk performance benchmarks. (3 replies, 03/26/87)
Who needs files? (0 replies, 03/26/87)
summery of references about memory management systems on micros (0 replies, 03/27/87)
Workshop Graphics Hardware (0 replies, 03/30/87)
Using a DMA chip in strange ways (18 replies, 03/30/87)
String Processing Instructions (1 reply, 03/30/87)
sprintf return value (0 replies, 03/30/87)
byte ordering? (0 replies, 03/31/87)
String Processing Instruction -- AMD 29000 has *slow* byte access (1 reply, 03/31/87)
String Processing Instruction -- printf, strcpy. (1 reply, 03/31/87)
Cordic Method (1 reply, 04/01/87)
String instructions; info on 4.3BSD ls (0 replies, 04/01/87)
Opus 64 continues ...... (0 replies, 04/01/87)
Whetstone & Linpack numbers wanted (2 replies, 04/02/87)
textbooks for an intermediate computer architecture course (0 replies, 04/02/87)
Performance Brief; Benchmarks for Zillions of Computers long (0 replies, 04/02/87)
Cordic chips (1 reply, 04/02/87)
comp.arch.par (1 reply, 04/02/87)
new Gould NPL (8 replies, 04/02/87)
new Gould NPL; Whetstone MIPS; Humpty-Dumpty (0 replies, 04/03/87)
new Gould NPL; Whetstone MIPS (1 reply, 04/06/87)
AMD 29000 byte access -- apology and further commentary (1 reply, 04/06/87)
IBM RAMP-C Benchmark (0 replies, 04/07/87)
Gould NP1 (7 replies, 04/07/87)
XEROX Dragon processor (0 replies, 04/07/87)
Tuning your libraries for your machine (4 replies, 04/08/87)
Swapping and Paging (0 replies, 04/08/87)
varargs and register windows (3 replies, 04/09/87)
recent 386 timings from Intel (2 replies, 04/10/87)
Source of Doduc benchmark (0 replies, 04/10/87)
Seeking Session Chairs and papers for IEEE Compcon 1988 (0 replies, 04/10/87)
68020-Cache-Question (0 replies, 04/11/87)
NS32532 (10 replies, 04/12/87)
Previous posting NS32532 (0 replies, 04/12/87)
80386 32-Bit Multiply Problems? (1 reply, 04/13/87)
String Handling -- Incompetence of run-time libraries (16 replies, 04/15/87)
Update to word addressing (1 reply, 04/15/87)
locality of reference (0 replies, 04/15/87)
Dhrystones vs. Optimizing compilers (1 reply, 04/16/87)
Wrangling over 32532 claims (1 reply, 04/16/87)
unaligned accesses and words-versus bytes long, much data (2 replies, 04/17/87)
An idea I've been kicking around (0 replies, 04/17/87)
Slow simulations (0 replies, 04/17/87)
Questioning, not wrangling (2 replies, 04/17/87)
String Handling and run-time libraries (13 replies, 04/19/87)
Word vs. Byte Orientation (10 replies, 04/19/87)
Definition: Kludge - The Exact Quote (0 replies, 04/20/87)
String Handling (1 reply, 04/20/87)
String Handling -- strcpy (0 replies, 04/20/87)
Processor Design (0 replies, 04/21/87)
What is optimization? (0 replies, 04/21/87)
JSR (0 replies, 04/22/87)
NS32532 Patents (9 replies, 04/22/87)
Want help with netlib project (0 replies, 04/22/87)
Byte .vs. Word Alignment (2 replies, 04/22/87)
CPU Processing Power Needed? (0 replies, 04/23/87)
Word vs. Byte Orientation; some kernel #s (2 replies, 04/23/87)
"Unoptimizing" Dhrystone (8 replies, 04/23/87)
Branch Prediction Paper (0 replies, 04/23/87)
Anyone for memory management on the AM29000? (3 replies, 04/23/87)
8150, 3270, INS info wanted.. (0 replies, 04/25/87)
the NS32532 (24 replies, 04/25/87)
Request: Real World SPICE input files (0 replies, 04/25/87)
bit, byte, and word level addressing (1 reply, 04/26/87)
Optimization vs. the programmer (18 replies, 04/26/87)
Huge mass storage systems (0 replies, 04/27/87)
String Processing Instruction (52 replies, 04/27/87)
Definition: Kludge (14 replies, 04/27/87)
An idea I'm kicking around (18 replies, 04/28/87)
Life with TLB and no PT (3 replies, 04/28/87)
implementing shared libraries (7 replies, 04/28/87)
AM29000 memory management (5 replies, 04/28/87)
Am29000 TLB reload paper requests (0 replies, 04/29/87)
SUPERCOMPUTING CONFERENCE-ADVANCE P (0 replies, 04/29/87)
ARC on XENIX V/286 (0 replies, 04/29/87)
Acorn RISC Dhrystone benchmarks (1 reply, 04/30/87)
AM29000 MMU really MIPS TLB long (1 reply, 05/01/87)
Optical Computing (4 replies, 05/01/87)
New BBS Announcement Organization: The Pennsylvania State University From: <DLZ@PSUVMA (0 replies, 05/01/87)
Am29000 information toll free number (0 replies, 05/01/87)
easy question about intel 80186 (1 reply, 05/02/87)
Building a FORTH machine (0 replies, 05/02/87)
Klu (5 replies, 05/04/87)
More on MIPSco TLB (1 reply, 05/04/87)
More on MIPSco TLB Butler Lampson Reference (0 replies, 05/04/87)
Lampson's paper (0 replies, 05/04/87)
64 Vs 32 (72 replies, 05/05/87)
Words & Bytes (1 reply, 05/05/87)
Optical Interconnects (5 replies, 05/06/87)
Comp. Arch. Symp. Program (0 replies, 05/07/87)
AM29000 Memory System?? (0 replies, 05/07/87)
Am29000 information toll free numbe (0 replies, 05/07/87)
Booleans (0 replies, 05/07/87)
AM29000 Booleans numbers; long (2 replies, 05/07/87)
Comparison Data (0 replies, 05/07/87)
new news group proposal... (0 replies, 05/08/87)
Cloning the new IBMs without violating copyrights (14 replies, 05/09/87)
Branch prediction in the 532 (14 replies, 05/10/87)
386 pipeline details (2 replies, 05/10/87)
Hypercubes (14 replies, 05/11/87)
Performance of the 532 (5 replies, 05/11/87)
Ideas for coprocessor protocol (4 replies, 05/11/87)
What's the fastest clock chip? (2 replies, 05/13/87)
68851 PMMU and 68030 MMU (1 reply, 05/13/87)
Branch prediction (0 replies, 05/13/87)
Multiply as Shift-Add (3 replies, 05/13/87)
AM29000 Booleans (10 replies, 05/13/87)
Packed Decimal on VAX (0 replies, 05/15/87)
Whetstone benchmark in FORTRAN wanted (0 replies, 05/15/87)
Doduc benchmark posted to net.sources (0 replies, 05/15/87)
80286 vs. 432 (2 replies, 05/15/87)
Optimizing multiplies (0 replies, 05/15/87)
Fun addressing modes (0 replies, 05/15/87)
Fujitsu RISC ?? (2 replies, 05/15/87)
Benchmark Timing (2 replies, 05/15/87)
Distributed Discrete Event Simulation (0 replies, 05/17/87)
05/18/87 Dhrystone Benchmark (1 reply, 05/18/87)
Do every object based systems suffer from poor performance ? (5 replies, 05/19/87)
Benchmarking Systems' Performance (0 replies, 05/19/87)
Branch Target Cache vs. Instruction Cache (3 replies, 05/19/87)
I-cache prefetch (2 replies, 05/19/87)
Performance of LISP machines (0 replies, 05/20/87)
Processing (21 replies, 05/20/87)
Bad Dhrystone results (0 replies, 05/20/87)
Software Page Table Machines (4 replies, 05/20/87)
Wanted: Hardware support for Object-Oriented systems (0 replies, 05/20/87)
Comment about Benchmark horse races you can change the world (0 replies, 05/21/87)
Japanese 32-bit CPUs (24 replies, 05/21/87)
68020 speeds and wait states (5 replies, 05/21/87)
The COM -- an object-oriented architecture (0 replies, 05/22/87)
bc benchmarks (0 replies, 05/22/87)
To RISC or to CISC ..... (5 replies, 05/22/87)
really CISC (3 replies, 05/22/87)
IOCALL Benchmark Results (0 replies, 05/23/87)
NS32332 cache support? (0 replies, 05/23/87)
32-bit CPUs (6 replies, 05/26/87)
SCSI DRIVER (0 replies, 05/27/87)
Benchmarking ...really Nelson benchmarks (3 replies, 05/28/87)
Benchmarking the 532, 68030, MIPS, 386...at a Usenix! (22 replies, 05/28/87)
can't send a reply (0 replies, 06/01/87)
Benchmarking Considered Harmful (0 replies, 06/02/87)
Question: on-chip or off-chip MMU? (26 replies, 06/02/87)
Seeking Benchmarking Tools (0 replies, 06/02/87)
Benchmarking and Realities of the Marketplace (0 replies, 06/02/87)
Profilers (0 replies, 06/02/87)
wanted: multi processor system information (0 replies, 06/03/87)
Calculating logs and exponentials (1 reply, 06/05/87)
vendor LAN and UniForum (2 replies, 06/06/87)
multi-valued logic, usefulness of (0 replies, 06/07/87)
Calculating log, exp, and CORDIC - summary (0 replies, 06/08/87)
ETA (1 reply, 06/08/87)
Prototype clock/compiler quality `benchmark' soon (0 replies, 06/09/87)
Benchmarking ...really Compiler flames (3 replies, 06/09/87)
Transputers (2 replies, 06/09/87)
Social Issues in Benchmarking Bake-offsi (0 replies, 06/09/87)
Interrupt vectors. (12 replies, 06/10/87)
NS32532 questions (1 reply, 06/10/87)
Social Issues in Benchmarking Bake-offs (4 replies, 06/11/87)
Hazards of Benchmarking & Job security... (0 replies, 06/11/87)
number bases (1 reply, 06/11/87)
ETA? (6 replies, 06/12/87)
Benchmarking the 532 ... (0 replies, 06/14/87)
Info needed on NCR 32/800 (2 replies, 06/15/87)
What is the "Neal Nelson&Associates Business Benchmark" ? (0 replies, 06/15/87)
Simulation eating mips (1 reply, 06/15/87)
Pipelines (0 replies, 06/16/87)
vliw comuputers (1 reply, 06/18/87)
More Futurebus Info (0 replies, 06/19/87)
Other advantages of ternaries (3 replies, 06/19/87)
Request hypercube machine information (1 reply, 06/20/87)
PC7300 VM - anyone know? (0 replies, 06/22/87)
IOCALL Benchmark Results Summary and Source (1 reply, 06/22/87)
CDC Wrens on Suns (1 reply, 06/25/87)
NEC V60 CPU (0 replies, 06/25/87)
Programs for Distributed/Multiprocessor Systems (0 replies, 06/26/87)
CORDIC references (3 replies, 06/26/87)
chewing up mips (1 reply, 06/26/87)
TLB consistency on shared-memory MIMD multiprocessors (1 reply, 06/29/87)
Simulation Eats Up MIPS (1 reply, 07/01/87)
comp.arch.par - Free gifts- Read (4 replies, 07/01/87)
chewing up mips with graphics (22 replies, 07/02/87)
More benchmark numbers wanted for Performance Brief (1 reply, 07/02/87)
benchmark numbers (0 replies, 07/02/87)
The 80386 is not upward compatible with the 8086! (1 reply, 07/02/87)
Simulation eats MIPS (1 reply, 07/02/87)
Partial clock/compiler quality characterizer (0 replies, 07/03/87)
Added note characterizer (0 replies, 07/03/87)
SPICE / floating-point benchmarks (0 replies, 07/04/87)
SPICE benchmarks: measurements (0 replies, 07/04/87)
chewing up mips with graphics [ (0 replies, 07/04/87)
Applications for consuming processor power (2 replies, 07/06/87)
Eighth Computer Arithmetic Symposium (0 replies, 07/07/87)
IEEE floating point modes (10 replies, 07/07/87)
Is binary decomposition fastest? (0 replies, 07/07/87)
Emulex periperals work on Sun-3's! (0 replies, 07/07/87)
Parallel Processing - References (1 reply, 07/07/87)
Letting goodies slip? (2 replies, 07/08/87)
Hypercube Survey response (0 replies, 07/08/87)
Iocall benchmark results for Plexus P/95!! (0 replies, 07/09/87)
comp.arch.par-no more Tshirts (1 reply, 07/09/87)
Kernel build times, esp. on Amdahl (4 replies, 07/09/87)
chewing up mips with graphics parallel computing (6 replies, 07/09/87)
parallel computing (2 replies, 07/13/87)
location and dates for the 1988 Architecture Conference (1 reply, 07/13/87)
XENIX 386 benchmark results (4 replies, 07/15/87)
Neural Networks (0 replies, 07/16/87)
IOCALL Results summary (0 replies, 07/17/87)
Help! Need some numbers fast on VAXen (0 replies, 07/18/87)
Shared memory with virtual caching (0 replies, 07/18/87)
CRT memories, summary of email answers to net, and thanks (0 replies, 07/20/87)
CRT memories: how do you write zero? (0 replies, 07/21/87)
Why make up names (0 replies, 07/22/87)
Power-of-2 (1 reply, 07/22/87)
VME/SCSI <--> voice products (0 replies, 07/22/87)
Mailing list on modeling/simulation of networks (0 replies, 07/24/87)
Word and subword sizes (2 replies, 07/24/87)
The Power of **2 (2 replies, 07/27/87)
The winner! (1 reply, 07/28/87)
machine word sizes (4 replies, 07/28/87)
Phys vs Virtual Addr Caches (18 replies, 07/28/87)
Radix-50 and namei (0 replies, 07/28/87)
Size of SysV "block" (21 replies, 07/30/87)
An old fashioned memory technology, CRT's, how'd they work? (11 replies, 07/30/87)
Architecture behind "early" electronic calculators (2 replies, 07/31/87)
Dhrystone replacement. Info req. (0 replies, 08/02/87)
Fork handling in reverse mapped maps, was Re: Phys vs Virtual Addr Caches (0 replies, 08/02/87)
Dhrystone Report (0 replies, 08/02/87)
dhrystone benchmark (2 replies, 08/02/87)
Need help (0 replies, 08/03/87)
Sun-4 Floating-Point Performance (0 replies, 08/04/87)
What with these Vector's anyways? really string ops (1 reply, 08/04/87)
Database machines - prospects, mgt, etc (0 replies, 08/04/87)
Architecture behind early electronic calculators (1 reply, 08/05/87)
Disk Striping on CM (1 reply, 08/05/87)
IMSL test (0 replies, 08/06/87)
simulation & the i386 bug (2 replies, 08/06/87)
Addendum to comment about classes from Sid Fernbach (0 replies, 08/08/87)
Dhrystone results (1 reply, 08/08/87)
What do know about Motorola 8000/100? (0 replies, 08/10/87)
What is with these Vectors anyways? (3 replies, 08/10/87)
WANTED: Unified operating system for Sun/uVax II & 2000 (1 reply, 08/11/87)
Request for input on Unix VM schemes (0 replies, 08/13/87)
IMSL results (0 replies, 08/13/87)
Dhrystones & string ops Was vectors (2 replies, 08/14/87)
Parallel Code for Shared Memory Machines (1 reply, 08/14/87)
Disk speed, was Re: Disk Striping (0 replies, 08/15/87)
Hydrogen filled disk drives (0 replies, 08/16/87)
*Why* do modern machines mostly hav (5 replies, 08/17/87)
Intel quote on 386 Multiply bug (0 replies, 08/17/87)
Book Reviews on Parallel Computation (0 replies, 08/18/87)
In reply to Paul W. on Neural Networks (0 replies, 08/18/87)
New book on RISC architecture - anyone see it? (0 replies, 08/18/87)
Bibliography on parallelism (0 replies, 08/18/87)
Optical mass storage (0 replies, 08/19/87)
*Why* do modern machines mostly have 8-bit bytes? (30 replies, 08/19/87)
Higher transfer-rate disks (2 replies, 08/19/87)
*Why* do modern machines mostly have 8-bit bytes (1 reply, 08/20/87)
Needed: MC6502-Int. Struct. Desc. (0 replies, 08/20/87)
Will the real 10 mips machine please stand up? (3 replies, 08/20/87)
Addressing registers in register file architectures. (0 replies, 08/23/87)
Disk striping reference from 1977 (0 replies, 08/24/87)
Technical graphics (0 replies, 08/24/87)
mach my day (1 reply, 08/24/87)
a tetrabyte at a gigabyte per second (1 reply, 08/25/87)
how fast could disks be (9 replies, 08/25/87)
Public Digital Radio Service wireless modem proposal (0 replies, 08/25/87)
Gratuitous bashing of everyone's favorite monopoly (0 replies, 08/25/87)
optical disks (2 replies, 08/25/87)
Helium (0 replies, 08/26/87)
Disk rotational speed vs. striping vs. parallel heads (4 replies, 08/26/87)
unix history refs (1 reply, 08/26/87)
Between a Sun-4 and a Cray-2 (8 replies, 08/26/87)
80386 Multiply: quote from Intel (4 replies, 08/26/87)
FSF and processor bigotry (0 replies, 08/27/87)
Weitek 8064 (0 replies, 08/27/87)
was 360 (0 replies, 08/27/87)
MIPS Floating Point processor. (2 replies, 08/27/87)
Faster disks (1 reply, 08/27/87)
Pipelining a VAX (1 reply, 08/28/87)
super new UNIX machine -- but are the disks fast enough? (1 reply, 08/28/87)
Questions on Optical Computers (0 replies, 08/28/87)
Addressing registers (0 replies, 08/28/87)
Mach, the new standard? GNU + MACH == true_love (1 reply, 08/28/87)
ASPLOS-II ADVANCE PROGRAM (0 replies, 08/29/87)
The 360 was a design landmark (24 replies, 08/31/87)
Was the 360 badly-designed? (46 replies, 09/01/87)
BBC Computer (2 replies, 09/02/87)
The minute Barrier (1 reply, 09/02/87)
micros vs. minis for timesharing (0 replies, 09/02/87)
What with these Vector's anyways? (32 replies, 09/03/87)
ASPLOS-II REGISTRATION NEWS FLASH! (0 replies, 09/03/87)
NC4016 (1 reply, 09/04/87)
Mach on the Microvax II, Vaxstation 2000 and Sun 3/50 (0 replies, 09/04/87)
Some comments on the NEC V60/V70 (1 reply, 09/04/87)
386/387 floating point benchmarks (0 replies, 09/04/87)
Am29000 Master/Slave Checking (0 replies, 09/04/87)
`small is beautiful' (0 replies, 09/05/87)
Fastest Kernel Make (5 replies, 09/06/87)
QM-1 or like machines??? (17 replies, 09/07/87)
Newsgroup for Parallelism (2 replies, 09/08/87)
brash micros ... [really: CPI versus (3 replies, 09/09/87)
MIPS wars (0 replies, 09/10/87)
Hardware : The Next Generation ... (1 reply, 09/11/87)
Computers: The New Generation (2 replies, 09/11/87)
More on Newsgroup for Parallelism. (0 replies, 09/12/87)
386 demand paged virtual memory (5 replies, 09/13/87)
A Good Document: "HP 9000 Series 800 Performance Brief" (0 replies, 09/13/87)
Compatibility with EBCDIC (2 replies, 09/14/87)
360 vs VAX stuff (5 replies, 09/14/87)
DRam errors (0 replies, 09/15/87)
SPICE benchmark input files (0 replies, 09/15/87)
Mach, the new standard? (25 replies, 09/15/87)
Discussions about FSF, GNU, Minix, etc. (0 replies, 09/15/87)
wetware (0 replies, 09/16/87)
Spurious Rumours (1 reply, 09/17/87)
Benchmark results using SPICE (2 replies, 09/17/87)
real-time and apollo (2 replies, 09/18/87)
Who owns Unix (17 replies, 09/18/87)
DRAM ECC on-chip. Won't Handle Whole-row Stuck-at Faults? (0 replies, 09/18/87)
Disk Striping still! (0 replies, 09/18/87)
8086 Unix, was Re: FSF (0 replies, 09/19/87)
FSF (1 reply, 09/20/87)
Monolithic vs Modular (1 reply, 09/21/87)
csh hacks for distrib. proc. system - where did I read this? (0 replies, 09/21/87)
Big [COMPLEX] Programs Hurt Performance (0 replies, 09/21/87)
Relative Speed (0 replies, 09/21/87)
SASI/SCSI References wanted (0 replies, 09/22/87)
S.i.B. (0 replies, 09/22/87)
Amdahl's Law (5 replies, 09/22/87)
Answers to Amdahl's Law (0 replies, 09/22/87)
Error Correcting dRAM chips (0 replies, 09/22/87)
Prentice Hall Manuals (0 replies, 09/22/87)
09/20/87 Dhrystone Patch01 (0 replies, 09/24/87)
Distinction between concurrent, distributed and parallel processing (0 replies, 09/24/87)
need data on process sizes (0 replies, 09/25/87)
IBM/36 questions (0 replies, 09/25/87)
Virtual memory operating system for PDP-11 (0 replies, 09/25/87)
09/20/87 Dhrystone Results (3 replies, 09/26/87)
Sampling (1 reply, 09/26/87)
VLSI Implementation of ECC (0 replies, 09/26/87)
VLIW Seminar in Mechanical Engineering (0 replies, 09/28/87)
brash micros versus the Big Iron: not yet (43 replies, 09/28/87)
D-machine helped spawn RISC (17 replies, 09/29/87)
The 18th Int'l Sym. on Fault-Tolerant Computing (0 replies, 09/29/87)
shared memory vs nonshared memory vs protocols (0 replies, 09/29/87)
minix (0 replies, 09/30/87)
Transcendental functions and microcoded instructions (2 replies, 09/30/87)
info needed about Nubus (1 reply, 10/01/87)
Cray Research walkout (1 reply, 10/01/87)
looking for VLIW references (1 reply, 10/01/87)
request: Old Iron performance (1 reply, 10/01/87)
Power vs number of circuits (3 replies, 10/02/87)
Implementing extended (0 replies, 10/02/87)
brash micros versus the Big Iro (0 replies, 10/02/87)
Pronunciation Guide Please (10 replies, 10/02/87)
RISC Architecture Survey (0 replies, 10/02/87)
Unix File System Performance (9 replies, 10/03/87)
386 unix (11 replies, 10/03/87)
98% in < 2s (4 replies, 10/05/87)
Looking for video disc (0 replies, 10/05/87)
Stacks and Parameters (0 replies, 10/05/87)
Superbus Study Group (0 replies, 10/06/87)
SIMULA compiler source needed (0 replies, 10/07/87)
Using the SCSI interface (1 reply, 10/07/87)
register windows [really: varargs} (0 replies, 10/07/87)
Big Programs Hurt Performance (24 replies, 10/07/87)
Steve Chen resigning (5 replies, 10/07/87)
Experience with Analog Devices ADSP2100 and /or RTI-980 (0 replies, 10/08/87)
request for info about weird varargs implementations (0 replies, 10/08/87)
Demand paged virtual memory (5 replies, 10/08/87)
Cray Shakeup, etc. (1 reply, 10/09/87)
Divides (7 replies, 10/10/87)
FP: software vs. hardware (2 replies, 10/12/87)
Definition of "virtual memory" (2 replies, 10/12/87)
Free Software Foundation (72 replies, 10/12/87)
Small is beautiful (11 replies, 10/12/87)
A novel compromise between simple and complex commands (1 reply, 10/13/87)
b (0 replies, 10/13/87)
c (0 replies, 10/13/87)
What should be in hardware but isn't (30 replies, 10/13/87)
PLEASE! (0 replies, 10/14/87)
MULTIFLOW SEMINAR (0 replies, 10/15/87)
Wanted 3-D graphics system in C for Mac. (0 replies, 10/15/87)
Double-bit errors and ECC memory (26 replies, 10/15/87)
Intel 432 (0 replies, 10/16/87)
What should be in hardware but isn' (5 replies, 10/16/87)
Sort Co-Processors (14 replies, 10/16/87)
GNU Security (5 replies, 10/18/87)
VM, Paging, Demand Paging (7 replies, 10/19/87)
IOStone: A Synthetic File System Performance Benchmark (0 replies, 10/20/87)
2nd Call For Papers: 15th Computer Architecture (0 replies, 10/20/87)
A Shared Libraries Solution (3 replies, 10/20/87)
Large programs (7 replies, 10/21/87)
RISC Survey Articles (6 replies, 10/22/87)
pipes (0 replies, 10/26/87)
Shared libraries (43 replies, 10/26/87)
Interconnection Networks (0 replies, 10/27/87)
Cache on a 286 board ? (2 replies, 10/27/87)
OS co-processor ?? (7 replies, 10/28/87)
Instruction cache for AMD 29000 (2 replies, 10/28/87)
smalltalk bytecode usage (0 replies, 10/28/87)
SCAT45 (0 replies, 10/28/87)
FPS T Series (2 replies, 10/29/87)
Something for parallel processing (0 replies, 10/29/87)
OS Coprocessor Research (0 replies, 10/30/87)
pseudo terminals (0 replies, 10/30/87)
"fork" with no MMU (2 replies, 10/30/87)
ZS-1 (2 replies, 10/31/87)
PDP-11/55's still running strong (1 reply, 11/02/87)
H/W Write Buffers, S/W Synchronizat (1 reply, 11/02/87)
Serial Search Machines (5 replies, 11/02/87)
MIPS Performance Brief, zillions of numbers, very long (2 replies, 11/03/87)
pdp-11/45 (1 reply, 11/04/87)
register windows Really Stack machines/stack-caches (1 reply, 11/04/87)
MIPS Performance Brief - errata (0 replies, 11/04/87)
Benchmarking in a High Level Language (3 replies, 11/04/87)
ETA10-P performance (0 replies, 11/05/87)
Performance Measurement and Dataflow Architectures (0 replies, 11/05/87)
1100/80 is not an "early UNIVAC" was (0 replies, 11/05/87)
Benchmark standard machine (1 reply, 11/06/87)
SUPERCOMPUTING CONFERENCE (0 replies, 11/06/87)
VME/68020 Multiprocessor boards (3 replies, 11/06/87)
History of base registers (0 replies, 11/07/87)
paging in the terminal driver (22 replies, 11/07/87)
Computer Math Book (3 replies, 11/07/87)
concurrent process synchronization help (0 replies, 11/08/87)
Adders in the register access path (0 replies, 11/10/87)
Stack Architectures (0 replies, 11/10/87)
Windowed register speeds: critical path? (0 replies, 11/10/87)
Towards A Meaningful Performance Measure (15 replies, 11/11/87)
Alliant FX/8 Info Requested (0 replies, 11/11/87)
ETA10-P (0 replies, 11/11/87)
Computer Math Books (0 replies, 11/12/87)
MIPS Performance Brief: improvements to Sun-4 MIPS UNIX numbers (0 replies, 11/12/87)
Ackermann on M/500 and Sun-4 (0 replies, 11/13/87)
H/W Write Buffers, S/W Synchronization (8 replies, 11/13/87)
Half-Cache (0 replies, 11/13/87)
FPS T-Series (1 reply, 11/14/87)
Why only half a cache? (0 replies, 11/16/87)
Content Addressable Memory (1 reply, 11/16/87)
H/W Write Buffers, S/W Synchron (0 replies, 11/16/87)
CRISP arch. details (0 replies, 11/16/87)
MIPS register handling question (2 replies, 11/16/87)
SPARC vs CRISP (0 replies, 11/17/87)
wanted: stats on Pascal pgms (0 replies, 11/17/87)
The pot calling the kettle black (0 replies, 11/18/87)
Needed : functional simulator for RISC type architecture (0 replies, 11/18/87)
Messed up previous message! (0 replies, 11/18/87)
VME-Multibus Adapter (0 replies, 11/19/87)
Chip Area Distribution in Processors (3 replies, 11/19/87)
Proposed news group comp.sys.unisys (0 replies, 11/19/87)
Macho flops versus Megaflops (5 replies, 11/19/87)
Arithmetic Traps in 29000 (1 reply, 11/19/87)
arch. info. request (4 replies, 11/19/87)
SPARC (1 reply, 11/19/87)
myths & magazines (3 replies, 11/19/87)
Runtime checks (0 replies, 11/20/87)
Saxpy Matrix-1 (0 replies, 11/20/87)
Information Request: Sun's SPARC Chip (12 replies, 11/20/87)
Looking for info on Weitek chip (1 reply, 11/21/87)
Multiprocessing Benchmark Desired (0 replies, 11/23/87)
Striking a few more SPARCs :-} (1 reply, 11/23/87)
UNIX benchmarks (0 replies, 11/23/87)
Fairchild Clipper performance? (6 replies, 11/24/87)
Historical correction (1 reply, 11/24/87)
Information Request (0 replies, 11/24/87)
HZ (2 replies, 11/25/87)
MIPS ratings of old machines (4 replies, 11/26/87)
Pyramid Register Set (0 replies, 11/26/87)
UNIX fork (7 replies, 11/28/87)
Horizontal Pipelining -- a pair (2 replies, 11/30/87)
OS/2 (1 reply, 11/30/87)
Why I want an integer overflow mode bit (1 reply, 12/01/87)
Why/why-not an integer overflow mode bit (0 replies, 12/02/87)
*-VME bus repeaters (4 replies, 12/02/87)
Systolic Arrays (10 replies, 12/03/87)
Wirth's "challenge" (16 replies, 12/03/87)
Why/why-not an integer overflow (0 replies, 12/05/87)
Horizontal pipelining (24 replies, 12/06/87)
div and mod (0 replies, 12/09/87)
Multiprogramming and demand paging (0 replies, 12/10/87)
job search, Comp. eng. (0 replies, 12/10/87)
Simple query (5 replies, 12/12/87)
SRAMS vs. cache-cihps (1 reply, 12/13/87)
SPARC slow? MIPs fast? (0 replies, 12/16/87)
Zilog Z320 32-bit chip (7 replies, 12/16/87)
silicon limits (0 replies, 12/16/87)
Why is SPARC so slow? long, more data (0 replies, 12/17/87)
MIPS and LIPS (1 reply, 12/18/87)
Stack Computer References (2 replies, 12/18/87)
null-terminated strings are OK (0 replies, 12/21/87)
Text-to-Voice Convertor (0 replies, 12/21/87)
Why is SPARC so slow? (22 replies, 12/22/87)
DEC Performance Methodology (0 replies, 12/22/87)
Cooperative versus Competitive Multitasking (0 replies, 12/23/87)
Brain-Clogging Decimal (7 replies, 12/24/87)
Single tasking the wave of the futu (8 replies, 12/25/87)
C machine (17 replies, 12/28/87)
machine specific languages (2 replies, 12/28/87)
hardware mask for tagged addresses (0 replies, 12/29/87)
Thinking about parallelism (0 replies, 12/29/87)
Requests for info; gremlins in the mail; try again (0 replies, 12/29/87)
Wanted info on Lisp machines (0 replies, 12/29/87)
Cache Evaluation Benchmarks. (1 reply, 12/30/87)
Single tasking the wave of the future? (28 replies, 12/30/87)
Am29000 Reg-Reg Moves? (0 replies, 12/31/87)
Comp. Arith. Conf.: When? (0 replies, 01/01/88)
pdp-11/55 (42 replies, 01/01/88)
Gate counts for implementations of architectures (1 reply, 01/01/88)
Parallel v. vector (0 replies, 01/02/88)
multi-tasking is alive and well (4 replies, 01/03/88)
ROM (0 replies, 01/04/88)
Wirth's challenge (9 replies, 01/05/88)
Multi Tasking query (0 replies, 01/05/88)
Single/Multi Tasking position summary (8 replies, 01/06/88)
Parallelism Definitions (1 reply, 01/06/88)
Why is SPARC so slow? [long, mo (2 replies, 01/06/88)
Request for DSP based Master's Thesis ideas.... (0 replies, 01/06/88)
Virtual Busses & Distributed MMUs (0 replies, 01/07/88)
Suggestions for a fault tolerant computer. (0 replies, 01/08/88)
ROM Unix (0 replies, 01/08/88)
Am29000 Reg-Reg Move? (2 replies, 01/09/88)
Request for reading material (0 replies, 01/09/88)
Null-terminated C strings (18 replies, 01/09/88)
"Life" benchmarks (7 replies, 01/10/88)
Simulator vs Emulator (1 reply, 01/10/88)
taken -vs- untaken branches (9 replies, 01/12/88)
A Grading for Benchmarking (0 replies, 01/12/88)
Impossible 40MHz R2000 ?? (8 replies, 01/12/88)
Request for Dhyrstone benchmark results (0 replies, 01/12/88)
Slow CD ROMS? (0 replies, 01/13/88)
Read Only Root FS (0 replies, 01/13/88)
CD-ROM speed (3 replies, 01/13/88)
SIMD bit serial arrays (0 replies, 01/14/88)
**FREE** Prime 250 (3 replies, 01/14/88)
a thought provoking note on RISC processors (3 replies, 01/14/88)
CD-ROMS (0 replies, 01/15/88)
giving the compiler advice (0 replies, 01/15/88)
Branching (0 replies, 01/15/88)
68020 - Indirect Post-indexed (2 replies, 01/15/88)
the comma operator and other comments (0 replies, 01/15/88)
base 10 float hardware (3 replies, 01/15/88)
Refereces on bus structures (0 replies, 01/15/88)
profiler changing source (0 replies, 01/16/88)
Sun/3 and Sun/4 (0 replies, 01/17/88)
A case for FREQUENCY statements (0 replies, 01/18/88)
What Jerry Pournelle knows about computers (1 reply, 01/19/88)
taken -vs- untaken branches, Fo (6 replies, 01/20/88)
386 & snoopy caching (0 replies, 01/21/88)
IBM 360 floating point round off problems (0 replies, 01/21/88)
Numerical Computation Newsgroup needed? (9 replies, 01/21/88)
Unix in ROM [was Re: Jerry Pournelle on UNIX (4 replies, 01/21/88)
FREQUENCY statements: fill a much-needed gap (8 replies, 01/22/88)
Yearly survey: Top ten of parallel processing (0 replies, 01/22/88)
more on parallel processing (0 replies, 01/22/88)
Round-off (10 replies, 01/23/88)
Convex Architecture (0 replies, 01/23/88)
2 computers enough for US (0 replies, 01/23/88)
taken -vs- untaken branches, Fortran FREQUENCY declaration (10 replies, 01/27/88)
Mail reply problems (0 replies, 01/28/88)
Intel 432's evolves into a RISC??? (5 replies, 01/29/88)
RISC criteria (1 reply, 01/29/88)
R/O root (9 replies, 01/29/88)
Frequency (1 reply, 01/29/88)
Super Chip Designers Wanted was (0 replies, 01/30/88)
Question about ESDI Disk Controllers (4 replies, 01/30/88)
|| execution (0 replies, 01/30/88)
Sun/3 and Sun/4 - Email summary (1 reply, 01/31/88)
Performance increase - a suggestion really RISC FP (0 replies, 01/31/88)
Counterexample to the 50% axiom (0 replies, 01/31/88)
comp.numeric deferred; try Stanford NA list (3 replies, 02/02/88)
ISSCC micoprocessor papers (0 replies, 02/02/88)
Cerberus multiprocessor simulator (0 replies, 02/02/88)
Machine-specific vs. Machine-independent code (0 replies, 02/02/88)
X data communications conventions (0 replies, 02/03/88)
The NeXT Machine? (0 replies, 02/04/88)
Wanted: BAR CODE reader for PC (0 replies, 02/04/88)
super multipliers (3 replies, 02/05/88)
Latest Dhrystone numbers (0 replies, 02/05/88)
sun's new mips honesty (2 replies, 02/06/88)
Parallel processing `top ten' (0 replies, 02/06/88)
protocol copies (0 replies, 02/07/88)
Jerry Pournelle on UNIX (34 replies, 02/07/88)
ITS translations: security problem? (5 replies, 02/08/88)
single vs double float (2 replies, 02/08/88)
Motorola MC68881/68882 Manual published by Prentice-Hall (2 replies, 02/09/88)
Intel VGA chips from IBM designs (0 replies, 02/09/88)
CE multi-computer interface + simulator (0 replies, 02/09/88)
Motorola MC68881/68882 Manual publi (0 replies, 02/09/88)
ITS translations: security prob (1 reply, 02/10/88)
comp.parallel (4 replies, 02/10/88)
Bay Area talk on SPARC (0 replies, 02/10/88)
Motion to change "comp.hypercube" to "comp.parallel" (0 replies, 02/11/88)
Sun 4/60? (6 replies, 02/11/88)
Weird symbolic links... (0 replies, 02/11/88)
Dollar arith on 32 bit machines; NCR Century & 399 Query (0 replies, 02/11/88)
VLIWs/FPS (0 replies, 02/12/88)
432 (0 replies, 02/13/88)
"Watchdogs" (2 replies, 02/16/88)
Cray Whets anyone? (0 replies, 02/16/88)
data alignment (0 replies, 02/17/88)
The advantages of FREQUENCY (5 replies, 02/18/88)
NeXT Rumors... (4 replies, 02/19/88)
Information wanted on Actors (1 reply, 02/19/88)
Machines Seymour Cray has designed (1 reply, 02/19/88)
CFP - Parallel Programming (0 replies, 02/19/88)
IEEE FP Verification Suite? (0 replies, 02/20/88)
structures are ordered (0 replies, 02/20/88)
Performance increase - a suggestion (39 replies, 02/21/88)
Approaches to computer system performance (6 replies, 02/22/88)
Why make word size a power of two? (4 replies, 02/22/88)
target caching (3 replies, 02/22/88)
Condition Codes in General Registers (15 replies, 02/23/88)
Parallel Processing (1 reply, 02/23/88)
Self timed processors (5 replies, 02/23/88)
CORE ISA (0 replies, 02/23/88)
Multiple indexed data sizes (0 replies, 02/24/88)
Expressiveness of operations for a virtual machine (0 replies, 02/24/88)
44-bit 370 virtual addressing (4 replies, 02/25/88)
RISC data alignment (28 replies, 02/25/88)
More than 32 bits needed where? (45 replies, 02/25/88)
8036 counter/timer chip (2 replies, 02/25/88)
68882 (2 replies, 02/26/88)
Marketing MIPS (9 replies, 02/26/88)
How much is enough? (1 reply, 02/26/88)
Cache memory algorithms (0 replies, 02/26/88)
2 good reasons for doing self-timed logic (0 replies, 02/26/88)
Cycle stretching (22 replies, 02/27/88)
Extra Precision Survey Summary (0 replies, 02/27/88)
TRON Architecture (3 replies, 02/28/88)
Harvard RISC (1 reply, 02/28/88)
RPM-40, Transputer PREFIX, HP auto-shifted registers (0 replies, 02/29/88)
Condition Codes in General Regi (3 replies, 03/01/88)
kit wishlist and software (0 replies, 03/01/88)
conditional branches (23 replies, 03/01/88)
RPM40 (2 replies, 03/01/88)
Editing on Crays (2 replies, 03/02/88)
Auto-shifted registers (11 replies, 03/02/88)
16 & 32 bit vs 32 bit only instruct (2 replies, 03/02/88)
What's Significant about Harvard Architecture? (2 replies, 03/02/88)
Dhrystones, anyone? (0 replies, 03/02/88)
Another benchmark request (1 reply, 03/02/88)
edge-vectors (0 replies, 03/02/88)
RPM-40 (1 reply, 03/02/88)
RPM40 questions (0 replies, 03/03/88)
Kanji processing (0 replies, 03/03/88)
Prefix instructions (3 replies, 03/03/88)
Array representation and language dependencies (1 reply, 03/03/88)
Shift and Subtract is NOT Multiply (3 replies, 03/03/88)
SPARC and the Slow Multiply Instruction (1 reply, 03/04/88)
TRON information (0 replies, 03/04/88)
Query respond by mail (0 replies, 03/04/88)
self-modifing code (1 reply, 03/04/88)
This is not the Kartashev Conference (0 replies, 03/04/88)
Task synchronization in multiprocessors? (2 replies, 03/04/88)
overflow in optimized multiplication (0 replies, 03/04/88)
RPM-40 microprocessor @ 40 MHz; data from ISSCC (13 replies, 03/04/88)
vectors on cheaper machines (0 replies, 03/05/88)
single unit pricing on uProcessors (0 replies, 03/05/88)
Bad RISC (7 replies, 03/05/88)
Code size vs. Data size (1 reply, 03/05/88)
Cray 2 has 2GW address (14 replies, 03/05/88)
conversion algorithm, floating pt formats (2 replies, 03/05/88)
Longer quote, RPM-40 performance (12 replies, 03/05/88)
RISC processor in new Apollo system (2 replies, 03/06/88)
Remote editing (3 replies, 03/07/88)
MIPS, VIPS, and VUPS (0 replies, 03/08/88)
Powers of 2, was Re: RISC is a nasty no-no! (3 replies, 03/09/88)
Supercomputer addresses (0 replies, 03/09/88)
Split IN and OUT Data Bus Tradeoffs (2 replies, 03/09/88)
RPM-40 really forwarding (3 replies, 03/09/88)
A weird angle on the bank-hit problem (0 replies, 03/10/88)
2-D arrays (5 replies, 03/10/88)
Was: RISC is a nasty no-no! Mor (2 replies, 03/10/88)
Yield of core-MIPS chips (2 replies, 03/10/88)
WARNING: Two bugs in Dhrystone 2.0 (2 replies, 03/10/88)
Dhrystone 2.0 (5 replies, 03/10/88)
reusing registers (0 replies, 03/11/88)
Time synchronization in a Distributed Environment (7 replies, 03/11/88)
Supercomputer addresses and language use (1 reply, 03/11/88)
standard size names (10 replies, 03/11/88)
RPM-40 microprocessor @ 40 MHz; dat (30 replies, 03/12/88)
Futurebus status (1 reply, 03/12/88)
multiphase clocks vs. MHz (0 replies, 03/12/88)
Was: RISC is a nasty no-no! More to the point: Supercomputer addresses (10 replies, 03/14/88)
Motorola RISC Chip (0 replies, 03/14/88)
Memory bank conflicts (3 replies, 03/14/88)
comp.hypercube -> comp.parallel (2 replies, 03/14/88)
New RISC from Motorola (1 reply, 03/14/88)
CPU chip cache sizes, was Re: Harvard Architecure (3 replies, 03/17/88)
MC68030 addvertisement;really: truth is stranger than marketing (0 replies, 03/17/88)
RISC is a nasty no-no! (41 replies, 03/18/88)
Advance Program 15th Intl. Symp. Computer Architecture (0 replies, 03/18/88)
Sticky overflow (9 replies, 03/18/88)
GCC, SUN LD, suggestions about debugging multiprocessors (1 reply, 03/19/88)
Type Conversions (1 reply, 03/22/88)
Architectural analysis of RPM-40 for general usage very long (6 replies, 03/22/88)
RISC Microcontrollers (0 replies, 03/22/88)
Expose Floating Point Internals (0 replies, 03/23/88)
VAX MIPS VUPS (0 replies, 03/23/88)
To interlock or not to interlock (0 replies, 03/23/88)
Cray-3 ? (2 replies, 03/24/88)
Cache lookahead (5 replies, 03/24/88)
Prefix and Trap Addressibility (1 reply, 03/24/88)
16 & 32 bit vs 32 bit only instructions for RISC. (29 replies, 03/24/88)
Info needed on Navier-Stokes machine (0 replies, 03/24/88)
read (1 reply, 03/25/88)
Cache coherency schemes (0 replies, 03/25/88)
Architectural analysis of RPM-40 for general usage (4 replies, 03/25/88)
Chen's claim (1 reply, 03/25/88)
History of parallel computation (0 replies, 03/25/88)
Harvard Architecure (13 replies, 03/25/88)
Big programs on workstations (1 reply, 03/26/88)
Memory Management for Large Memories (0 replies, 03/26/88)
Sun-3/50 speed variations (1 reply, 03/26/88)
crossposting (1 reply, 03/26/88)
MC68030 addvertisement (2 replies, 03/27/88)
Tasting of Dhrystone 2.0 Results (10 replies, 03/28/88)
Architectural analysis of RPM-40 fo (0 replies, 03/28/88)
Sparse vectors (0 replies, 03/28/88)
misc arch features requested (0 replies, 03/29/88)
Dusty decks (1 reply, 03/29/88)
Architectures/Languages (0 replies, 03/30/88)
TF-1/RP3 was Languages vs. machines The need for D-scussion (0 replies, 03/30/88)
Karp challenge (1 reply, 03/30/88)
FORTRAN horrors (0 replies, 03/30/88)
MIPS R3000 (0 replies, 03/30/88)
Lights on computers (2 replies, 03/30/88)
Languages vs. machines (3 replies, 03/30/88)
Vector machines (2 replies, 03/30/88)
Hardware Support for High Speed Graphics Computations (2 replies, 03/31/88)
Any experience/comments with Multiflow machines? (0 replies, 03/31/88)
Hardware description languages as H/W engineer tool. (0 replies, 04/01/88)
Computer noises not sampling (0 replies, 04/01/88)
Motorola 88000 info wanted (0 replies, 04/01/88)
Average Program Size (1 reply, 04/01/88)
Commercial MIPS-X (2 replies, 04/01/88)
Yield of core-MIPS chips MIPSCo yield? && Other Issues (10 replies, 04/02/88)
Sandia's parallelism speedups (1 reply, 04/02/88)
Cache Terminology? (4 replies, 04/02/88)
What's a Vax 11/780 MIP really? (10 replies, 04/03/88)
IBM 704 nostalgia (1 reply, 04/05/88)
gee whiz lights (0 replies, 04/05/88)
Radiation Hardening Chips (2 replies, 04/06/88)
MIPS R3000??? (3 replies, 04/06/88)
Yet another dumb question (3 replies, 04/07/88)
Why build TF-1 if you have its uniprocessor chips? (5 replies, 04/07/88)
FORTRAN Horror (34 replies, 04/08/88)
Proposal for Nanotechnology group (0 replies, 04/08/88)
Speed of computer vs. appearance of its user (0 replies, 04/08/88)
Protectionism (4 replies, 04/08/88)
The Bellcore divider (1 reply, 04/09/88)
For a good time, read... (8 replies, 04/09/88)
How fast are your disks? (6 replies, 04/09/88)
Reminders for Old Hands (0 replies, 04/09/88)
GATT declares U.S. - Japan chip pac (1 reply, 04/10/88)
GATT declares U.S. - Japan chip pact illegal (36 replies, 04/11/88)
longjmp (2 replies, 04/11/88)
Press Release: Intel announces 8096 (0 replies, 04/11/88)
R3000 (0 replies, 04/12/88)
Motorola 88000 and others (7 replies, 04/14/88)
NaN and INF in non-IEEE (0 replies, 04/14/88)
Yield of core-MIPS chips [MIPSCo yield? && Other Issues] **LONG!** (1 reply, 04/14/88)
sizeof behavior (1 reply, 04/15/88)
Fortran summary (2 replies, 04/15/88)
Computer noises (24 replies, 04/15/88)
IEEE Micro Review of new Toshiba TRON chip (0 replies, 04/15/88)
{char foo[]="This is a test."; printf (0 replies, 04/15/88)
Yield of core-MIPS chips [MIPSC (0 replies, 04/16/88)
Cray architecture (25 replies, 04/16/88)
RFS vs. NFS (43 replies, 04/16/88)
Is the 80960 a supercharged 432? (0 replies, 04/17/88)
Nitpicking on Steve's explanation of 960 instruction speeds (0 replies, 04/17/88)
VME + private bus (0 replies, 04/17/88)
Bit Addressable Architectures (32 replies, 04/18/88)
MMU and/or external abort on 80376/80960? (1 reply, 04/18/88)
Press Release: Intel announces 80960 architecture (28 replies, 04/18/88)
80960 Dhrystones 1.1 (0 replies, 04/18/88)
Sofware cache control for RISC chip sets (1 reply, 04/19/88)
80960 "stack frame cache" - multiple register sets (0 replies, 04/20/88)
Motorola 88000 (0 replies, 04/20/88)
RISC floating point coprocessors (8 replies, 04/21/88)
Measurement (0 replies, 04/22/88)
Sofware cache control for RISC chip (0 replies, 04/22/88)
80960 Register windows (2 replies, 04/23/88)
To R.M. Owens / Pyramid=No Risc (1 reply, 04/23/88)
Descriptions of various important machines (0 replies, 04/25/88)
IBM3330 (0 replies, 04/25/88)
hard data on Motorola 88000 (3 replies, 04/26/88)
Crazed Physicist (0 replies, 04/26/88)
RAM Question: (6 replies, 04/27/88)
debugging on a VLIW machine (3 replies, 04/27/88)
Missing SPARC instruction? (1 reply, 04/27/88)
Wulf's WM (5 replies, 04/27/88)
3D Graphics Algorithms (0 replies, 04/27/88)
All things to all people? (0 replies, 04/28/88)
Request for info on Mini-super computers (0 replies, 04/28/88)
Fast 432 (2 replies, 04/29/88)
Tell me what to do with my IBM 4955! (1 reply, 04/29/88)
SUMMARY of non-IEEE NaN and INF (0 replies, 04/29/88)
Need information of benchmarks (0 replies, 04/30/88)
Alliant FX series (0 replies, 04/30/88)
references and papers on file systems wanted. (0 replies, 05/01/88)
Proposed architecture characterization survey form (27 replies, 05/02/88)
Comp. Architecture survey (1 reply, 05/02/88)
Curb feelers (11 replies, 05/02/88)
Comp. Architecture & Organization (6 replies, 05/04/88)
Intel RISC CPU/80486 : do they exist ? (2 replies, 05/04/88)
Intel 80960, Memory Mgmt, and Military parts (2 replies, 05/05/88)
CCI's new RISC-based system (0 replies, 05/05/88)
ARM chips (1 reply, 05/06/88)
Fast dividers? (0 replies, 05/06/88)
Universal OS & universal language (5 replies, 05/06/88)
Universal Programming Languge (0 replies, 05/06/88)
PL/I is assembler?? (0 replies, 05/06/88)
[is] RISC a short answer?? (0 replies, 05/06/88)
mail trouble (0 replies, 05/06/88)
Cost of Low-end RISCS for RTC (1 reply, 05/06/88)
True Horror Stories (0 replies, 05/06/88)
The WM Machine (6 replies, 05/07/88)
Computer Architecture and Organization (4 replies, 05/07/88)
Amdahl 5990 benchmarks (0 replies, 05/07/88)
Survey of architectures was (18 replies, 05/07/88)
RISC registers (0 replies, 05/08/88)
Instruction scheduling on a VLIW machine (1 reply, 05/09/88)
Do RISC Compilers Consider Multipro (5 replies, 05/10/88)
ZFOD before COW (2 replies, 05/10/88)
80960 IO (5 replies, 05/10/88)
Benchmark names: origins (0 replies, 05/10/88)
Disk drives -- speed of? (12 replies, 05/10/88)
Automatic Shutdown (1 reply, 05/11/88)
virtual cache coherency (2 replies, 05/11/88)
CRAY COMPUTERS (1 reply, 05/11/88)
Universal OS (25 replies, 05/12/88)
hardware support of reference and change bits (4 replies, 05/12/88)
Unix machines for large databases (19 replies, 05/12/88)
Unsigned arithmetic (0 replies, 05/13/88)
CISC strikes back. (7 replies, 05/14/88)
info on ieee/acm microprogramming conf needed (0 replies, 05/14/88)
68000 Assembler/Interpreter Desperately Needed (0 replies, 05/16/88)
unsigned / addresses (0 replies, 05/17/88)
Do RISC Compilers Consider Multiprogramming? (8 replies, 05/18/88)
RISC != real-time control (29 replies, 05/18/88)
hardware for late-binding languages (3 replies, 05/18/88)
Is the Intel memory model safe from (1 reply, 05/18/88)
Is the Intel memory model safe from NO-ONE ?!? (43 replies, 05/18/88)
Fortran Follies (3 replies, 05/18/88)
User mode trap handlers (1 reply, 05/18/88)
Hardware-supported user handlers: examples (2 replies, 05/19/88)
Today's dumb question... (20 replies, 05/19/88)
HELP ME!!! (0 replies, 05/19/88)
Writable Microcode (1 reply, 05/19/88)
RISC != Real Time Control (0 replies, 05/20/88)
RISC a short answer?? (28 replies, 05/20/88)
Hot New Machines (0 replies, 05/20/88)
Japanese 32-bit micro can be a 6802 (1 reply, 05/20/88)
General purpose commercial multiprocessor systems without shared-memory (3 replies, 05/21/88)
microprogrammable machines (0 replies, 05/22/88)
competing (1 reply, 05/23/88)
RTX-2000 Demo and Rochester Forth Conference (0 replies, 05/24/88)
Zero divide trapping to kernel mode (0 replies, 05/24/88)
architecture/implementation form (0 replies, 05/24/88)
architecture/implementation -- MIPS (0 replies, 05/24/88)
Dhrystone compilation times - major correction (0 replies, 05/24/88)
Intel memory model (2 replies, 05/24/88)
1988 Rochester Forth Conference (0 replies, 05/25/88)
Japanese 32-bit micro can be a 68020 or 80386 (28 replies, 05/25/88)
Info on IBM RP3 wanted (0 replies, 05/25/88)
Writable Microcode: programmable gate arrays (1 reply, 05/25/88)
integer multiplies (2 replies, 05/25/88)
SPARC and multiprocessing (30 replies, 05/25/88)
3rd IC Supercomputer (0 replies, 05/25/88)
typical programs (1 reply, 05/27/88)
SUMMARY: multiprocessor systems without shared-memory (0 replies, 05/27/88)
Book: FORTRAN on Supercomputers (0 replies, 05/28/88)
Intel RISC <> 80960 : true or false ? and 80486 (1 reply, 05/29/88)
88k cache details (1 reply, 05/29/88)
virtual I/O (2 replies, 05/29/88)
How did this program burn out two monitors? (12 replies, 05/29/88)
Info. on SPARC (1 reply, 05/29/88)
Chaining routines, sequencers (1 reply, 05/31/88)
Is Shared Memory Necessary? (10 replies, 05/31/88)
Stack Architectures Can Have Registers (3 replies, 05/31/88)
Course on Real Time Control Software techniques. (0 replies, 05/31/88)
Random thoughts on paging. (3 replies, 06/01/88)
Query on properties/performance measures in parallel/distrib environment. (0 replies, 06/01/88)
architecture/implementation -- 88000 (4 replies, 06/02/88)
88k register sets? (4 replies, 06/02/88)
volatile (22 replies, 06/02/88)
How did this program burn out two m (1 reply, 06/02/88)
WISC info (0 replies, 06/03/88)
RAM-based microcode machine (0 replies, 06/03/88)
Dhrystone compilation times (6 replies, 06/03/88)
RISC vs CISC on Low-End Processors (10 replies, 06/03/88)
I need the paper describing fast BitBlts. (0 replies, 06/04/88)
1 TFLOPS commercially available when? (0 replies, 06/04/88)
Info. wanted on implementations of distributed applications (0 replies, 06/05/88)
*r*off (0 replies, 06/06/88)
Real Time Unix (0 replies, 06/06/88)
PDP-10 user I/O (16 replies, 06/06/88)
more on unsigned (3 replies, 06/07/88)
6/13 10am Alan Huang (0 replies, 06/08/88)
VM vs Supercomputers (0 replies, 06/09/88)
88000 port of Mach? (0 replies, 06/10/88)
VM needed for rapid startup (26 replies, 06/10/88)
SIGPLAN Papers (0 replies, 06/10/88)
Changing times (1 reply, 06/11/88)
Fwd: 88000 port of Mach? (0 replies, 06/12/88)
3rd party OS (3 replies, 06/13/88)
IEEE FP Test Suite (0 replies, 06/13/88)
Details on Moto 88200 CMMU: correction (0 replies, 06/14/88)
iPSC Mailing List (0 replies, 06/14/88)
Native MIPS > VAX MIPS (0 replies, 06/14/88)
Native MIPS vs VAX MIPS (0 replies, 06/15/88)
Details on Moto 88200 CMMU (4 replies, 06/15/88)
Cretinous status/control register access (3 replies, 06/16/88)
Maximum MIPS for a given memory ban (3 replies, 06/16/88)
Crippled RISC - Call for Vendors (0 replies, 06/16/88)
The VAX Always Uses Fewer Instr (0 replies, 06/17/88)
Maximum MIPS for a given memory bandwidth? (18 replies, 06/17/88)
negative addresses (60 replies, 06/17/88)
VAX 11 years after (0 replies, 06/17/88)
Algol 60 vs Algol 68 (4 replies, 06/17/88)
Crippled RISC (0 replies, 06/17/88)
the other Unisys machines (5 replies, 06/18/88)
Parallel Lisps for Parallel Machines (0 replies, 06/18/88)
Branch Delay Annullment (10 replies, 06/20/88)
why people create write-only registers (3 replies, 06/21/88)
Lightning Fast Photonic Optical Computers (1 reply, 06/21/88)
[Wrt Zuse] Re: Info wanted on eniac computers (0 replies, 06/21/88)
More On Write-Only Control Register (0 replies, 06/22/88)
Goodbye (0 replies, 06/22/88)
stack machines (11 replies, 06/23/88)
More On Write-Only Control Registers (6 replies, 06/23/88)
pad grid package (2 replies, 06/23/88)
microprocessor dates and technology (0 replies, 06/24/88)
Intel announces P9 as 80386SX (4 replies, 06/24/88)
Optimizing Assemblers (0 replies, 06/24/88)
Definition of "imprecise interrupt" (0 replies, 06/24/88)
several concurrent memory ops (1 reply, 06/24/88)
Info wanted on eniac computers (4 replies, 06/25/88)
Why no disks with two HDAs ? (9 replies, 06/25/88)
Compiler complexity (6 replies, 06/26/88)
Request for simulation packages (0 replies, 06/28/88)
optimizing asms (1 reply, 06/28/88)
1 TFLOP Tally (0 replies, 06/28/88)
IBM RISC patents - long (0 replies, 06/28/88)
m88k memory stalls (1 reply, 06/28/88)
`RISC-based' (0 replies, 06/29/88)
IBM RISC patents (4 replies, 06/30/88)
Eternal RISC v CISC (0 replies, 06/30/88)
Clippinger-modified ENIAC and June 48 Manchester Mark I (1 reply, 06/30/88)
What can you do with a 1 million gate EPLD. (0 replies, 07/01/88)
VAX 8??? vs Motorola 88000 (0 replies, 07/01/88)
fft routine (0 replies, 07/03/88)
ASPLOS: `Superoptimiser' (0 replies, 07/03/88)
no-branch 68000 signum, min, max (1 reply, 07/05/88)
Bifurcated Pipelines (0 replies, 07/05/88)
88k speed on FP add/neg/mov (0 replies, 07/06/88)
Memory latency / cacheing / scientific programs (20 replies, 07/06/88)
The VAX Always Uses Fewer Instructions (16 replies, 07/07/88)
dhrystone benchmark listing (1 reply, 07/07/88)
10 registers are enough (0 replies, 07/08/88)
M88000 Benchhmarks (0 replies, 07/08/88)
System Performance as a Function of Memory Characteristics (0 replies, 07/09/88)
Average MIPS ratings (0 replies, 07/09/88)
getting rid of branches (14 replies, 07/09/88)
RISC as the making of UNIX (0 replies, 07/10/88)
IBM and RISCy Business (3 replies, 07/10/88)
IBM Demands License Fees for RISC (2 replies, 07/11/88)
Should be "supercomputer history" . Was: Re: Superoptimiser. (0 replies, 07/11/88)
Instruction Execution Timings for MicroVAX II needed. (0 replies, 07/11/88)
request for shared-memory parallel programs (0 replies, 07/11/88)
88k trick for FP abs/neg (5 replies, 07/12/88)
RISC machines and scoreboarding (31 replies, 07/12/88)
M88000 power dissipation as a function of programming (2 replies, 07/12/88)
Superoptimiser. (15 replies, 07/13/88)
MAC 88000 (0 replies, 07/13/88)
Intel Coprocessors (0 replies, 07/13/88)
Digital and Mips (0 replies, 07/14/88)
80x86 Measurement (1 reply, 07/15/88)
Gemini (3 replies, 07/15/88)
Floating-Point Indoctrination: Final Lecture (1 reply, 07/15/88)
Fancy indexing (0 replies, 07/15/88)
Dhrystone 2.1 discounts segment thrashing (2 replies, 07/15/88)
where can I get a copy of the IEEE floating point standards? (1 reply, 07/15/88)
special issue of CAN (0 replies, 07/15/88)
m88000 benchmarks (21 replies, 07/16/88)
Copying bytes quickly, was RISC bashing at USENIX (0 replies, 07/16/88)
more registers (0 replies, 07/16/88)
IBM Stretch (2 replies, 07/16/88)
Copying bytes quickly (0 replies, 07/16/88)
Programmed code generation (3 replies, 07/17/88)
Optimizers, dead code elimination (0 replies, 07/18/88)
Open Systems (0 replies, 07/18/88)
Bitblt chips and things (3 replies, 07/18/88)
Programmed code generation: Native vs. Pcode (5 replies, 07/19/88)
A question about direct-mapped caches (0 replies, 07/19/88)
Standard data formats (0 replies, 07/20/88)
Vectorising conditional code. (8 replies, 07/20/88)
A question about direct-mapped cach (0 replies, 07/21/88)
missing Dhrystone 2.1 (14 replies, 07/21/88)
strtod (0 replies, 07/21/88)
Looking for UNIX workloads (0 replies, 07/21/88)
Fast FP addition (1 reply, 07/22/88)
Big sieve results for SUN3 & SUN4 (1 reply, 07/22/88)
Standard Un*x H/W architecture (16 replies, 07/22/88)
3rd super mtg Boston references (0 replies, 07/23/88)
Boston super mtg VOLUME 2 (0 replies, 07/23/88)
Zilog Z80,000 (1 reply, 07/23/88)
HP2100 Origins (1 reply, 07/23/88)
Shifting question: m88k (2 replies, 07/24/88)
CRAY vs. caching & VM (1 reply, 07/24/88)
References on Event-Driven Programming? (0 replies, 07/25/88)
Costs of physical vs virtual caches (1 reply, 07/25/88)
users speak out (0 replies, 07/26/88)
VM, paging and fast vector machines (0 replies, 07/26/88)
Proxmire, one time only (0 replies, 07/26/88)
IBM Stretch rounding modes (1 reply, 07/26/88)
Shifting question (20 replies, 07/26/88)
Execute instructions (9 replies, 07/27/88)
Cray & Amdahl Virtual memory debate (4 replies, 07/27/88)
Software vs Hardware BitBlt (2 replies, 07/27/88)
Cray & Amdahl (15 replies, 07/28/88)
Shuttle software (0 replies, 07/29/88)
Execute instructions, Bit Blit, Self-modifying code, Programming in Assembler (3 replies, 07/29/88)
Scientific Virtual Memory (2 replies, 07/29/88)
IBM RISC patent No.s and titles (0 replies, 07/29/88)
RISC bashing at USENIX (22 replies, 07/29/88)
MC 88k question (1 reply, 07/29/88)
MC88000 multiply question (1 reply, 07/29/88)
Emulating an 8088 on a bit-slice (0 replies, 07/29/88)
Assembler curricula, was Re: using (0 replies, 07/29/88)
memory system design (1 reply, 07/29/88)
HP2100 (3 replies, 07/30/88)
compiler detection of potential run-time errors (2 replies, 07/30/88)
Cray (0 replies, 07/30/88)
machine architecture influence on memory copy code (0 replies, 08/01/88)
Pagefault time (2 replies, 08/02/88)
Blit (1 reply, 08/03/88)
Distributed processing (0 replies, 08/03/88)
Realstone benchmark (1 reply, 08/04/88)
Oops! (0 replies, 08/04/88)
assembler: lines of code (0 replies, 08/04/88)
meaning of MIPS (0 replies, 08/04/88)
IBM lawyers and the patent system (0 replies, 08/04/88)
Split I and D caches, IBM lawyers, and Motorola (1 reply, 08/04/88)
Apple & the 6502 (2 replies, 08/05/88)
I hate COMPASS (1 reply, 08/05/88)
THIS NEWSGROUP NEEDS SPLITTING. No, just cleaned up (0 replies, 08/07/88)
TOCS, articles (0 replies, 08/08/88)
sorry for double posting (0 replies, 08/08/88)
Goodbye again, see you next time... (0 replies, 08/08/88)
THIS NEWSGROUP NEEDS SPLITTING. (2 replies, 08/09/88)
transputers, and info on languages (0 replies, 08/09/88)
History of PCs, Any one rember the Sphere? (0 replies, 08/09/88)
R.I.P BYTE (2 replies, 08/09/88)
What's a "tahoe"? (8 replies, 08/10/88)
VAX Memory Test (8 replies, 08/10/88)
Is the 29000 in use yet? (1 reply, 08/11/88)
Blitters and design philosophy (10 replies, 08/11/88)
What's a "tahoe"? --- and the new bsd kernel memory allocator (2 replies, 08/11/88)
memories and destructive readout (0 replies, 08/11/88)
Dynamic RAM internals (1 reply, 08/11/88)
Risky instructions (4 replies, 08/11/88)
Dynamic RAMs (2 replies, 08/11/88)
transputer, etc. (0 replies, 08/11/88)
Architectural features for commercial DP (0 replies, 08/11/88)
IBM Technical Disclosure (0 replies, 08/11/88)
"scrubbing" (0 replies, 08/12/88)
Data General 1200 and the single/multiple processor debate (0 replies, 08/12/88)
Split I and D caches and IBM lawyers (17 replies, 08/12/88)
RCA 1802 (8 replies, 08/12/88)
History of personal computing (13 replies, 08/13/88)
Assembler Bogosity (1 reply, 08/13/88)
Hitachi S-820 (0 replies, 08/13/88)
The Concept of a "Cray on a Desk" (0 replies, 08/13/88)
Balanced system - a tentative definition (3 replies, 08/14/88)
HACF (0 replies, 08/14/88)
using assembler (10 replies, 08/15/88)
dedicated vs general-purpose CPUs (15 replies, 08/16/88)
lisp version of dhrystone benchmark (0 replies, 08/16/88)
attention to all those who helped... (0 replies, 08/16/88)
Balanced system - a tentative defin (3 replies, 08/16/88)
HACF.... now implemented on most systems... (0 replies, 08/17/88)
Definition of Fault Tolerant Architectures (3 replies, 08/17/88)
separate integer and float regi (0 replies, 08/17/88)
Unix on Supercomputers Workshop (0 replies, 08/18/88)
amusing opcodes (3 replies, 08/18/88)
Regarding shift-register-like memories (1 reply, 08/18/88)
nsieve benchmark (0 replies, 08/19/88)
separate integer and float register (8 replies, 08/19/88)
History of PCs (37 replies, 08/19/88)
Memory vector processor? (0 replies, 08/19/88)
real time clock chips (4 replies, 08/20/88)
Multiplying two shorts... (4 replies, 08/20/88)
Perils of comparison -- an example (3 replies, 08/20/88)
Sun f77 -fswitch overhead. Comparison with HP9000/350. (0 replies, 08/22/88)
Mips figures. (3 replies, 08/23/88)
using (52 replies, 08/23/88)
Sun 4 MIPS rating (8 replies, 08/24/88)
Topologix (0 replies, 08/25/88)
Participating on X3J11 (0 replies, 08/26/88)
A GaAs logic gate from S. Cray (0 replies, 08/26/88)
Moving floating point values around (7 replies, 08/26/88)
Inkstone (0 replies, 08/26/88)
IQFs (3 replies, 08/26/88)
RISC (6 replies, 08/27/88)
CISC instructions (4 replies, 08/29/88)
Third public review of X3J11 C (10 replies, 08/29/88)
Dedicated Processors (3 replies, 08/30/88)
Duff on i386 (0 replies, 08/30/88)
Index, 1988 Intl. Dist. Comp. Systems Conf. (0 replies, 08/30/88)
one large array in Pascal (6 replies, 09/01/88)
Sw vs. Hw BitBlit (32 replies, 09/01/88)
Checkered Benchmark History (2 replies, 09/02/88)
NSIEVE C Source File (5 replies, 09/02/88)
Multibus & CPU upgrades (0 replies, 09/02/88)
ISCA '89 WORKSHOPS - CALL for PROPOSALS (0 replies, 09/03/88)
WANTED: EXPERT-EASE SOFTWARE (0 replies, 09/04/88)
cancer, radiation, computing, & tomography (0 replies, 09/05/88)
separate integer and float registers (3 replies, 09/06/88)
FUSION product called NFSS, anyone use this with DEC VMS. (0 replies, 09/07/88)
cpu clock rates (0 replies, 09/07/88)
Loop unfolding (4 replies, 09/07/88)
Computer Organization Text Needed (10 replies, 09/07/88)
1989 Int. Conf. on Supercomputing (0 replies, 09/08/88)
Wanted: bus speed information, general survey (1 reply, 09/08/88)
IBM-801 Bytestring Move (0 replies, 09/09/88)
What is loop unfolding (0 replies, 09/09/88)
Need info on IEEE quad format (0 replies, 09/09/88)
Why Karnough? (2 replies, 09/12/88)
Request for RS-232 Port Usage (1 reply, 09/13/88)
Are all RISCs the same? (15 replies, 09/13/88)
Explanation, please! (36 replies, 09/14/88)
Elxsi, RISC/CISC tradeoffs (0 replies, 09/14/88)
Text For Computer Architecture Needed (0 replies, 09/14/88)
SMD Interface standard (5 replies, 09/14/88)
Exception handling (1 reply, 09/14/88)
Dartmouth College seeking to fill endowed chair in Computer Engineering (0 replies, 09/15/88)
cancer -- radiation therapy / early detection (0 replies, 09/15/88)
downloading a KXJ11 through an ELN node (0 replies, 09/16/88)
downloading a KXJ11 through an ELN uVAX node (0 replies, 09/16/88)
ICPP'88 references posted to comp.parallel (0 replies, 09/16/88)
K-map, etc. (0 replies, 09/16/88)
PDP-11 bus contention (2 replies, 09/16/88)
parallel processors (0 replies, 09/17/88)
PAWS/GPSM (1 reply, 09/20/88)
non-binary hardware (6 replies, 09/20/88)
Compilers that know about caches (0 replies, 09/20/88)
IEEE NEWS GROUP (3 replies, 09/20/88)
HP/Rumors (7 replies, 09/21/88)
Help: Hashing on TLB input? (4 replies, 09/21/88)
Help: Thrashing on TLB input? (0 replies, 09/21/88)
FYI - New Mac Disk Drives From Control Data Corp. (0 replies, 09/24/88)
FYI - New ETA 10 System From Control Data Corp. (0 replies, 09/24/88)
Logic Symbols Needed (0 replies, 09/26/88)
Workshop on Defect & Fault Tolerance at UMass, Oct 88 (0 replies, 09/26/88)
VHDL (0 replies, 09/27/88)
Pssst, Wanna start a rumor? (0 replies, 09/27/88)
downloading a KXJ11 on an ELN node from a VMS host (0 replies, 09/27/88)
Transputer based systems. (10 replies, 09/27/88)
386 Paging Problem (0 replies, 09/28/88)
What is this Chip ? (1 reply, 09/29/88)
memory speed & futurology (7 replies, 09/29/88)
software analogy (2 replies, 09/29/88)
Arit-9 Symposium (0 replies, 09/29/88)
phase logic (2 replies, 09/29/88)
Question about Caches in Sun/Vax (1 reply, 09/30/88)
New product, NS32532 based computer board (0 replies, 09/30/88)
Multiprocessor address traces (0 replies, 09/30/88)
Motorola's new addition.... (0 replies, 09/30/88)
How the Japanese will win the MIPS wars with SPARC (7 replies, 10/01/88)
block copy & VAX MOVC (3 replies, 10/03/88)
VME bus spec ambiguous ? (0 replies, 10/03/88)
Workstations are real-time was Re: Are all RISCs the same? (0 replies, 10/03/88)
What is MX-1/16? (0 replies, 10/03/88)
Titan mini-super computer by Advent (0 replies, 10/04/88)
NULL pointers (14 replies, 10/04/88)
RISC speed madness (0 replies, 10/04/88)
query: new disk drive for VAX (1 reply, 10/05/88)
PEP (1 reply, 10/05/88)
The Sun RAS/CAS patent (0 replies, 10/05/88)
call gates (0 replies, 10/07/88)
SPARC vs. MIPS (0 replies, 10/07/88)
RISCy Roundtable, November 2. (0 replies, 10/07/88)
Lazy Store/Reload (0 replies, 10/08/88)
correction to symposium notice (0 replies, 10/08/88)
Reverse Engineering (3 replies, 10/10/88)
88000 Floating Point Pipeline (0 replies, 10/10/88)
"Dribble Back" (0 replies, 10/11/88)
CRegs (0 replies, 10/11/88)
compiler generated run time checking (0 replies, 10/12/88)
Machine Independent Intermediate Language (0 replies, 10/12/88)
PEP: Page Execution Priviledge (16 replies, 10/13/88)
The NeXT machine (0 replies, 10/13/88)
Semantics (13 replies, 10/14/88)
Contiguous address spaces (0 replies, 10/14/88)
Sun RAS/CAS Patent, the real story? (0 replies, 10/14/88)
Info on C compilers for Motorola 88k (0 replies, 10/14/88)
Register Windows (54 replies, 10/14/88)
Recognizing benchmarks (1 reply, 10/15/88)
optical disk in NeXT (0 replies, 10/15/88)
Machine-independent intermediate la (0 replies, 10/16/88)
The 256MB optical disk. (0 replies, 10/17/88)
NeXt and sound (0 replies, 10/17/88)
NeXT: Edit newsgroup _and_ subject lines please folks! (0 replies, 10/17/88)
NeXT: edit newsgroup AND subject lines please! (0 replies, 10/17/88)
The NeXT Problem Disk Swapping (1 reply, 10/17/88)
NeXT Step/OSF (0 replies, 10/17/88)
Looking for a TRUE NeXT comparison (0 replies, 10/17/88)
1 GByte physical memories (0 replies, 10/18/88)
Use comp.sys.next for NeXT postings now (0 replies, 10/18/88)
The NeXT Cache (1 reply, 10/18/88)
The NeXT Problem [Disk Swapping (1 reply, 10/18/88)
IBM's PC and AT patents (0 replies, 10/18/88)
RISC vs. CISC- a very quick & dirty argument (0 replies, 10/19/88)
"Compatible" (1 reply, 10/20/88)
Transmission line (1 reply, 10/20/88)
NeXT software distribution... (2 replies, 10/20/88)
call gates, was PEP: Page Execution Priviledge (1 reply, 10/20/88)
RC25 based Microvax-II systems (0 replies, 10/20/88)
"CISC MIPS" ... was "The NeXT Problem" (2 replies, 10/20/88)
Info on Software Analysis Workstation with 386 (0 replies, 10/20/88)
NeXT press release (7 replies, 10/20/88)
ECL at Tektronix (0 replies, 10/20/88)
"interprocedural analysis useless f (2 replies, 10/21/88)
Inappropreate??? Why? (1 reply, 10/21/88)
Remodeling, Needs Assessment (0 replies, 10/21/88)
The NeXT Problem, and NuBus in general (0 replies, 10/21/88)
Disassembling was Re: Machine-independent intermediate languages (2 replies, 10/21/88)
single-cycle 680X0 (2 replies, 10/22/88)
Vax Hax (0 replies, 10/22/88)
The NeXT machine has been announced! (60 replies, 10/23/88)
simplisticity quote: RISC v. CISC (1 reply, 10/23/88)
LISPMs not RISC? - Re: CISCy RISC? RISCy CISC? (3 replies, 10/23/88)
CMOS and ECL (0 replies, 10/23/88)
press clippings Re: The NeXT machine (7 replies, 10/24/88)
Big register files, the dominating RISC win? (1 reply, 10/24/88)
"interprocedural analysis useless for code optmization" (7 replies, 10/24/88)
CISCy RISC? RISCy CISC? (6 replies, 10/25/88)
RISC/CISC and the wheel of life. (3 replies, 10/25/88)
Cost of floptical s/w distribution (2 replies, 10/25/88)
NeXT articles don't belong in comp.sys.misc (3 replies, 10/25/88)
MIPS vs. SPARC (1 reply, 10/25/88)
Forget uMIILs -- why not an 'obfuscate' tool for C instead? (3 replies, 10/26/88)
The NeXT machine has been announced (1 reply, 10/26/88)
Intel announces new RISC system (1 reply, 10/26/88)
CMOS power consumption (0 replies, 10/26/88)
Apology (0 replies, 10/26/88)
Bar Wars again (4 replies, 10/26/88)
... why not an 'obfuscate' tool for C instead? (0 replies, 10/26/88)
Fairchild data books (0 replies, 10/27/88)
RISC vs mainframe (0 replies, 10/27/88)
communications problem (0 replies, 10/27/88)
future user interfaces (0 replies, 10/27/88)
The third G in 3G machines... (0 replies, 10/27/88)
Bigger process IDs and "dev_t"s (0 replies, 10/27/88)
Mainframe channels vs. DMA vs. NeXT (1 reply, 10/28/88)
Context Switch Time, A worst Case (1 reply, 10/28/88)
Nexxtus/NuBus revisited (0 replies, 10/29/88)
ISP wanted (1 reply, 10/29/88)
Some 1987 patents of interest (11 replies, 10/29/88)
LOOKING FOR A DATA GENERAL MV2000 (0 replies, 10/29/88)
MIPS Performance Brief 3.5, October 1988 more than long (2 replies, 10/30/88)
Longer load/store because of register windows (5 replies, 10/30/88)
multiple register windows (3 replies, 10/30/88)
Modular arithmetic, was Re: Trachtenberg System of Math (2 replies, 10/30/88)
Mainframe channels vs. DMA ... (0 replies, 10/30/88)
RT linkage convention (0 replies, 10/31/88)
WESTERN DIGITAL'S 286 BOARD (0 replies, 10/31/88)
ETA-10: CMOS or ECL? (16 replies, 10/31/88)
The magnetic/optical drive used in NeXT (0 replies, 11/01/88)
The 3G Machine (7 replies, 11/01/88)
How did they make the printer so cheap? (1 reply, 11/01/88)
CDC NOS vs. Mainframe channels vs. DMA vs. NeXT (0 replies, 11/01/88)
ASIC (4 replies, 11/01/88)
Software Distribution (62 replies, 11/01/88)
Some ARM data (1 reply, 11/02/88)
The NeXT Problem (56 replies, 11/02/88)
hypecubes and the connection machine (0 replies, 11/02/88)
RISC wars (0 replies, 11/03/88)
integer multiply (0 replies, 11/03/88)
Trachtenberg System of Math (7 replies, 11/03/88)
A request...***WARNING*** (2 replies, 11/03/88)
ARM (2 replies, 11/03/88)
HW sqrt/div (0 replies, 11/03/88)
A request... (2 replies, 11/04/88)
Universal Disassemblers vs. Universal MIILs (9 replies, 11/04/88)
info requested on Intel processor with a 33-bit word. (0 replies, 11/04/88)
mysterious socket (4 replies, 11/04/88)
division hashing (0 replies, 11/04/88)
Population count instruction (3 replies, 11/04/88)
Some facts about the Acorn RISC Machine (2 replies, 11/05/88)
Loss of Significance register (0 replies, 11/05/88)
more about division (2 replies, 11/05/88)
ETA-10 (4 replies, 11/05/88)
Multiprocessor RISC (5 replies, 11/06/88)
Problems with NeXT (4 replies, 11/06/88)
RISC v. CISC --more misconcepti (1 reply, 11/06/88)
Instruction timing (0 replies, 11/07/88)
NeXT Memory - No Error Checking or Parity ! (0 replies, 11/07/88)
AD chip does HW sqrt/div (0 replies, 11/08/88)
Universal Disassemblers vs. Univers (1 reply, 11/08/88)
Comiplers for RISC v. CISC (2 replies, 11/08/88)
RISC vs. CISC vs. RCC (2 replies, 11/09/88)
Object-code to object-code translation (0 replies, 11/09/88)
Myrias announces SPS-2 (0 replies, 11/09/88)
GE635 Gray to Binary (0 replies, 11/09/88)
Gray to Binary (0 replies, 11/09/88)
Machine-independent intermediate languages (25 replies, 11/10/88)
High Performance Mathematical Sieve (2 replies, 11/10/88)
RISC v. CISC --more misconceptions (29 replies, 11/11/88)
archimedes (0 replies, 11/11/88)
bit reversal instr/sw (0 replies, 11/12/88)
Available shared memory hardware (1 reply, 11/13/88)
60 Megahertz microprocessor? (2 replies, 11/14/88)
Questions about Myrias SPS-2 (0 replies, 11/14/88)
HW v. SW (12 replies, 11/14/88)
Binary compatability (0 replies, 11/15/88)
60 Megahertz Microprocessor (1 reply, 11/15/88)
Multiple level caches (0 replies, 11/15/88)
250 MHz SPARC implementation (2 replies, 11/16/88)
register save/restore (34 replies, 11/17/88)
Architecture Wars, again; survey (16 replies, 11/17/88)
Intel hypercube iPSC/2 with vector processor? (0 replies, 11/18/88)
IBM Vector Facility vs. Convex (0 replies, 11/18/88)
I/O rate measurements ? (0 replies, 11/19/88)
random notes from a John Mashey talk (0 replies, 11/19/88)
88k end-for-end routine (0 replies, 11/19/88)
Sun slowness (3 replies, 11/20/88)
Procedure Call Protocol (3 replies, 11/20/88)
SPEC contact (0 replies, 11/20/88)
Intel address (0 replies, 11/21/88)
Accurate results (0 replies, 11/21/88)
TMS320C30 (1 reply, 11/22/88)
scoreboards vs. Reg. tagging (0 replies, 11/22/88)
Restarting after virtual memory page fault (0 replies, 11/22/88)
Lisp "future" instruction in 88k hardware. (10 replies, 11/22/88)
Leading zero and pop count (10 replies, 11/22/88)
Why is the RT slow? (18 replies, 11/23/88)
object <-> object translation (5 replies, 11/24/88)
A simple question on RISC (41 replies, 11/24/88)
Supercomputers & FORTRAN Book (0 replies, 11/24/88)
CC machines do not execute 15% more instructions (0 replies, 11/24/88)
SPARC manuals (0 replies, 11/25/88)
Gates vs Transistors (5 replies, 11/26/88)
Common Compilers for benchmarks (11 replies, 11/27/88)
ks3 (0 replies, 11/28/88)
CFP 4th Int'l Conf. on Fault-tolerant Computer Systems (0 replies, 11/29/88)
Seeing the future (6 replies, 11/29/88)
OISC was Re: ZISC computers (3 replies, 11/29/88)
Looking for some articles on the Harvard Architecture (0 replies, 11/30/88)
Microchannel 'RT' at CMU (1 reply, 11/30/88)
Real Compiler for One Instruction Computer? (2 replies, 11/30/88)
Restart after page fault (0 replies, 11/30/88)
Memory-Mapped vs. Memory-Controlled (0 replies, 11/30/88)
Some statistics for Re: CC machines do not execute 15% more instructions (0 replies, 11/30/88)
CC machines do execute 15% more instructions (1 reply, 11/30/88)
Greenard's Algorithm (0 replies, 11/30/88)
Parallel Architecture Simulator (0 replies, 11/30/88)
Floating remainder (0 replies, 12/01/88)
ZISC computers (8 replies, 12/01/88)
New MIMD partitioning for FFTs (0 replies, 12/02/88)
penalty for microcode (5 replies, 12/02/88)
Sun-4/110 Performance Anomaly (0 replies, 12/03/88)
Memory-mapped floating point (6 replies, 12/03/88)
RISC v. CISC (73 replies, 12/03/88)
BENCHMARKS AND LIPS (8 replies, 12/03/88)
condition codes vs. compare/branch (1 reply, 12/03/88)
Is CRISP toast? (0 replies, 12/04/88)
Answer to Sun-4/110 Performance Anomaly (0 replies, 12/05/88)
Why no RISC clones? (5 replies, 12/06/88)
Why the original RT seemed/was slow (8 replies, 12/06/88)
I/O history and taxonomy (0 replies, 12/06/88)
The & (12 replies, 12/07/88)
Operating Systems (10 replies, 12/07/88)
Microprocessor kits wanted (0 replies, 12/07/88)
Dhrystone 2.1 (17 replies, 12/08/88)
Manchester Data Flow Machine (0 replies, 12/09/88)
88000 and VLIW (0 replies, 12/09/88)
88K table walk (9 replies, 12/13/88)
DSP96002 Motorola's Countach (0 replies, 12/15/88)
Hughes' 3-D Processor Array (3 replies, 12/15/88)
NS32532 table walk (0 replies, 12/15/88)
CAM hits the market (1 reply, 12/16/88)
Assembly or .... (50 replies, 12/18/88)
High FLOPS/buck machines (1 reply, 12/19/88)
Lawerence Livermore Loops in C (5 replies, 12/20/88)
Testability Features (9 replies, 12/20/88)
bus architecture research (0 replies, 12/20/88)
Where is Seymour's tongue? (2 replies, 12/20/88)
BSD vs. Sys V (0 replies, 12/20/88)
Revised I/O taxonomy (0 replies, 12/21/88)
A Recently Heard Story About Seymour Cray (15 replies, 12/21/88)
HP Precision Architecture Info (4 replies, 12/22/88)
80386 vs. 68030 (18 replies, 12/22/88)
Size of Plain Text (0 replies, 12/23/88)
parity/ecc (1 reply, 12/23/88)
Professional Programmers (8 replies, 12/25/88)
Professional Programmers and cos (0 replies, 12/27/88)
Intnl. Conf. on Supercomputing 89 (0 replies, 12/27/88)
Computing equipments for computing centers (0 replies, 12/27/88)
Info on intel microarchitectures (0 replies, 12/27/88)
GaA (2 replies, 12/28/88)
"fair" compilers (0 replies, 12/29/88)
VOLUNTEERS FOR IEEE COMPUTER SOCIETY (0 replies, 12/29/88)
Need DHRY 2.1 results (0 replies, 12/30/88)
looking for a few good RISC VME boards (3 replies, 12/31/88)
Multiple-Precision Operations (1 reply, 12/31/88)
SPARC supports 80- & 128-bit floats. So does MIPS. (0 replies, 01/01/89)
Range of IEEE floating point, >= 80 bits wide (0 replies, 01/02/89)
Cray SECDED (2 replies, 01/03/89)
"big endian" vs. "little endian" (0 replies, 01/03/89)
Performance comparision between minisupers (0 replies, 01/03/89)
A highly-recommended article on benchmarking (0 replies, 01/04/89)
questionable nos.--SPARC vs. MIPS on gcc (4 replies, 01/04/89)
Architecture Books and the Whereabouts of Glenford Myers (1 reply, 01/04/89)
"big endian" and "little endian" - first usage for computers (3 replies, 01/04/89)
SPARC vs. MIPS on gcc really, single-word refill (0 replies, 01/04/89)
GaAs Hardware (0 replies, 01/05/89)
Quadruple-Precision Floating Point (4 replies, 01/05/89)
questionable nos.--SPARC vs. MI (0 replies, 01/05/89)
"big endian" and "little endian" - the bottom line (0 replies, 01/05/89)
Help !! 68020 instruction analyzer needed. (1 reply, 01/05/89)
"big endian" string comparison (1 reply, 01/06/89)
MIPS supports 80- & 128-bit floats. (8 replies, 01/06/89)
IEEE floating-point on supercomputers (0 replies, 01/06/89)
SPARC @ 20 mips (2 replies, 01/06/89)
PARANOIA (0 replies, 01/06/89)
high density substrates (0 replies, 01/06/89)
Pointers to bus information (0 replies, 01/07/89)
bus-related questions in comp.arch and comp.periphs (0 replies, 01/07/89)
Accuracy results on various computers? (0 replies, 01/07/89)
Binaries and Max Speed (6 replies, 01/07/89)
SPARC vs. MIPS on gcc (17 replies, 01/07/89)
100 million native instructions/sec GaAs processor (0 replies, 01/08/89)
Cray Quotations (9 replies, 01/09/89)
Documentation NU and VME bus (3 replies, 01/09/89)
VME BUS Latency (0 replies, 01/10/89)
100 MHz GaAs processor (3 replies, 01/11/89)
Quadruple-Precision Floating Point ? (25 replies, 01/12/89)
CORE MIPS ISA Reference (0 replies, 01/12/89)
MIPS CORE ISA (1 reply, 01/12/89)
Cobol Data Corporation Cyber 180 (9 replies, 01/12/89)
on shells and os features (2 replies, 01/13/89)
Questions about New SUN machines. (0 replies, 01/13/89)
The scoop on the 80960 (1 reply, 01/14/89)
Saturn V Launcher (1 reply, 01/14/89)
APOLLO DN10010 (1 reply, 01/17/89)
Vertex coloring and register allocation (1 reply, 01/17/89)
Cray 1 Architecture Reference (0 replies, 01/17/89)
Sony NEWS, was DECstation 3100 info. (0 replies, 01/17/89)
Debugging amidst the endian wars. (0 replies, 01/18/89)
Synchronisation (2 replies, 01/18/89)
MIPS Architechture Question (4 replies, 01/18/89)
Wafer Scale Floating Point chip (4 replies, 01/18/89)
Shells everywhere (8 replies, 01/18/89)
DECstation 3100 vs ISC box (2 replies, 01/19/89)
Chaining on IBM 3090 VF (2 replies, 01/19/89)
N-Body Problem Reference (2 replies, 01/19/89)
another Intel chip rumor (1 reply, 01/19/89)
Metaflow SPARC Implementation (0 replies, 01/20/89)
Source for 68070 board (0 replies, 01/20/89)
Solid State Secondary Storage (17 replies, 01/20/89)
make sure you read latest IEEE Computer (1 reply, 01/20/89)
ABIs for new chips (1 reply, 01/20/89)
ABI, BMW, 386i (0 replies, 01/21/89)
Wanted refernces for Cray X-MP (0 replies, 01/22/89)
Paranoia benchmark (2 replies, 01/23/89)
interconnect tech/wsi (0 replies, 01/23/89)
BMW (0 replies, 01/23/89)
Rx000 byteorder (4 replies, 01/23/89)
"big endian" and "little endian" (2 replies, 01/24/89)
Wanted: SPARC machine language prog (4 replies, 01/24/89)
Transputer (1 reply, 01/24/89)
Hardware cache in a PC (0 replies, 01/24/89)
Sony Workstation (0 replies, 01/25/89)
Bubbles (10 replies, 01/25/89)
Request for classic problems and open questions. (0 replies, 01/25/89)
CFT/CFT77 gotcha (0 replies, 01/25/89)
Request for benchmark results (0 replies, 01/25/89)
DECstation 3100 info. (53 replies, 01/26/89)
Public Domain simulator wanted. (0 replies, 01/26/89)
"big endian" and "little endian" - first usage for computer (37 replies, 01/27/89)
computer security (0 replies, 01/27/89)
RAM Disks are obsolete (6 replies, 01/27/89)
Quantum Transitors (1 reply, 01/27/89)
Does anybody know of a maker of fault tolerant unix systems? (0 replies, 01/27/89)
Quantum Interconnects (2 replies, 01/28/89)
Intel's N-10: 150 MIPS? (1 reply, 01/29/89)
register saving (0 replies, 01/29/89)
TI announcement (17 replies, 01/30/89)
Question for 8255 Guru (0 replies, 01/30/89)
Cache models and program behavior (1 reply, 01/30/89)
Cache models and program behavior references (1 reply, 01/31/89)
Endian wars - really 386 question (1 reply, 01/31/89)
CM (0 replies, 01/31/89)
Whither the TK70 (1 reply, 02/01/89)
68070 board (6 replies, 02/01/89)
Limits (0 replies, 02/01/89)
Unification of big and little endian architectures. (6 replies, 02/02/89)
M88k byteorder selection (0 replies, 02/02/89)
Content Addressible Memories (25 replies, 02/02/89)
Looking for "SIMPLE" code (2 replies, 02/02/89)
Signetics 68070 (0 replies, 02/02/89)
'big endian' and 'little endian' - first usage for computer (3 replies, 02/03/89)
Quantum Interconnects & FTL Signals #1 (2 replies, 02/03/89)
ATT codec info request (0 replies, 02/03/89)
argv limits (0 replies, 02/04/89)
In Circuit Emulator for PS/2 (0 replies, 02/04/89)
MP Serializability (0 replies, 02/05/89)
Endian wars - really 386 questi (4 replies, 02/05/89)
Modelling (0 replies, 02/06/89)
Dhrystones Benchmark ? (0 replies, 02/06/89)
built-in security features (16 replies, 02/07/89)
References to Cache and Program Models (0 replies, 02/07/89)
Excuse my ignorance (0 replies, 02/09/89)
BCPL Strings (0 replies, 02/09/89)
while (1 reply, 02/09/89)
Egg on my face for breakfast, crow for lunch, humble pie for dinner (2 replies, 02/09/89)
microprocessors, floating point, embedded controller, performance, I/O processor, graphics (0 replies, 02/10/89)
Stop already! (0 replies, 02/10/89)
wanted - C and/or Fortran source for 24-loop Livermore Loops (0 replies, 02/10/89)
RISC/CISC Paper (2 replies, 02/10/89)
String length (2 replies, 02/10/89)
2 PDP-11 Instructions geeeez.... (0 replies, 02/10/89)
Fujitsu SPARC Interlocks (2 replies, 02/11/89)
use of fork (0 replies, 02/11/89)
Process sizes on the NeXT (2 replies, 02/11/89)
risc object sizes; emperical results (1 reply, 02/11/89)
Endian wars (28 replies, 02/11/89)
Comp.arch OR Comp.lang.C? (1 reply, 02/11/89)
Dhrystone Benchmark, Ada Version 2.1 (0 replies, 02/11/89)
Noun use of `random' (0 replies, 02/12/89)
88K info (1 reply, 02/13/89)
how to get livermore loops code (0 replies, 02/14/89)
probabilistic memory reference string models (0 replies, 02/14/89)
Multi-Processor Serializability (16 replies, 02/15/89)
SPARC spec? (0 replies, 02/15/89)
"mips" info (0 replies, 02/15/89)
String length hardware (3 replies, 02/15/89)
String lengths (31 replies, 02/16/89)
What is your idea of an ideal specification development system? (0 replies, 02/16/89)
VME bus broadcasting? (1 reply, 02/16/89)
Looking for 88K info (1 reply, 02/16/89)
TI9900 software request (0 replies, 02/16/89)
Barrel processors & string ops (0 replies, 02/16/89)
D-cache usefulness (0 replies, 02/16/89)
Apple's use of A-line traps (0 replies, 02/17/89)
Scoop on Intel N-10? (0 replies, 02/17/89)
Moelcular Modeling Benchmarks (0 replies, 02/18/89)
Flexible Processors and Hardware (0 replies, 02/18/89)
RISC & context switches (16 replies, 02/18/89)
Where can I get the Stanford integer benchmarks? (0 replies, 02/18/89)
ISSCC (0 replies, 02/20/89)
More 88K articles (0 replies, 02/21/89)
Endian reversing with high level languages (0 replies, 02/21/89)
allocate-on-fault (0 replies, 02/21/89)
true and false in C (1 reply, 02/21/89)
Asynchronous Design (0 replies, 02/21/89)
Fun C typos (5 replies, 02/21/89)
Seen in the local paper. (0 replies, 02/22/89)
Pub info on VMEbus Systems wanted (0 replies, 02/22/89)
Want "top" for MIPS machine (0 replies, 02/22/89)
Info. on Cray X-MP (0 replies, 02/22/89)
Info wanted on Livermore Loops (0 replies, 02/22/89)
Bus History Units (2 replies, 02/22/89)
Performance implementations of symbolic languages (0 replies, 02/22/89)
"General-purpose" architectures and symbolic languages (5 replies, 02/23/89)
General-purpose architectures and symbolic languages (0 replies, 02/23/89)
garbage collection vs. caches (0 replies, 02/23/89)
pointers to functions? (0 replies, 02/23/89)
Stoned benchmarks and other naming conventions (0 replies, 02/23/89)
[HS]W interlocks (7 replies, 02/24/89)
hedging about Lisp & Caches -- your mileage will vary (0 replies, 02/24/89)
N-10 query (2 replies, 02/24/89)
Not-so RISCy (8 replies, 02/24/89)
In defense of (3 replies, 02/24/89)
VMEbus publications (1 reply, 02/25/89)
When is RISC not RISC? (25 replies, 02/25/89)
Final Program: ASPLOS-III (0 replies, 02/25/89)
evaluation of architectures (1 reply, 02/25/89)
quest for breakthroughs (20 replies, 02/25/89)
Good articles on the ETA-10? (0 replies, 02/26/89)
disk access references? (0 replies, 02/26/89)
In Search of Breakthroughs -- A reply (0 replies, 02/27/89)
Ballistic transport? (2 replies, 02/27/89)
History Question: Origin of fork (7 replies, 02/27/89)
N-10 info (0 replies, 02/27/89)
Intel Assembly Language (1 reply, 02/27/89)
In defense of the VAX (33 replies, 02/28/89)
Endian reversing MOVEs (20 replies, 02/28/89)
Endian reversiong MOVEs (0 replies, 02/28/89)
Motorola delimiters (0 replies, 02/28/89)
Architecture Simulation Tools. (1 reply, 02/28/89)
Context switch tasks (3 replies, 02/28/89)
A dumb idea for making data caches more useful (2 replies, 02/28/89)
Don't look back (24 replies, 02/28/89)
Peephole optimisation (3 replies, 03/05/89)
HP 9825A (0 replies, 03/08/89)
Was *this* the first RISC chip? (3 replies, 03/08/89)
HSC (1 reply, 03/10/89)
Duff's Device? (0 replies, 03/10/89)
Molecular Modeling Benchmarks (0 replies, 03/11/89)
rhealstone (24 replies, 03/12/89)
troff floating point (0 replies, 03/12/89)
?h*stone (0 replies, 03/13/89)
In defense of the HEP (0 replies, 03/13/89)
MIPS R2000 questions (1 reply, 03/13/89)
rhealstone - could we please stop this stone-walling? (0 replies, 03/13/89)
Uniprocessor vs. Multiprocessor architectures (0 replies, 03/14/89)
Looking for integrated microprocessor caches (0 replies, 03/14/89)
fiber (0 replies, 03/14/89)
"?*stones" (0 replies, 03/15/89)
Not bigger than a breadbox (0 replies, 03/15/89)
Josephson Junctions (1 reply, 03/15/89)
I/O and Filesystems for Parallel Computers (0 replies, 03/16/89)
Reference request (0 replies, 03/16/89)
i860 - A question about built-in test features (0 replies, 03/16/89)
thanks for information on microprocessor caches (0 replies, 03/16/89)
ICS 89 Registration Information (0 replies, 03/16/89)
FORTRAN Dhrystone for i860? NO; NEW PLAUSIBLE ANSWER; FLAMES (0 replies, 03/16/89)
i860 information (0 replies, 03/17/89)
I860 graphics performance (0 replies, 03/17/89)
How to make 2 workstations behave as 1?? (1 reply, 03/17/89)
So, can you really fab 10**6 transi (0 replies, 03/17/89)
April Fools Technojokes (0 replies, 03/18/89)
Picking I and D cache sizes (0 replies, 03/18/89)
Foreign languages (0 replies, 03/18/89)
i860 Multiprocessing (6 replies, 03/18/89)
Summary of responses to VME broadcast question (0 replies, 03/18/89)
interrupt handling (0 replies, 03/19/89)
PGA data sheets (1 reply, 03/19/89)
Cryo-refrigerators (5 replies, 03/20/89)
Multiflow Trace VUPS/MIPS/etc. (0 replies, 03/21/89)
t (0 replies, 03/21/89)
jhjhjh (0 replies, 03/21/89)
Virtual caches & PIDs (0 replies, 03/21/89)
So, can you really fab 10**6 transistors now? (7 replies, 03/21/89)
i860 and compilers (2 replies, 03/22/89)
Foreign languages/PhD Reqs (0 replies, 03/22/89)
Josephson Junction processors (2 replies, 03/22/89)
ryryryryry (0 replies, 03/22/89)
The unbearable fuzziness of 'architecture' (0 replies, 03/22/89)
foreign langauage requirements (4 replies, 03/22/89)
Just how misleading can isolated MIPS/MFLOPS numbers be? very. (0 replies, 03/22/89)
i860 CPU information (31 replies, 03/22/89)
CS grad programs (0 replies, 03/22/89)
foreign langauage requireme (0 replies, 03/22/89)
The origin of P and V. (0 replies, 03/23/89)
Intel/MIPS Dhrystone ratio (14 replies, 03/23/89)
i860 Dhrystones (18 replies, 03/23/89)
FIFTH ANNUAL COMPUTER SCIENCE SYMPOSIUM (0 replies, 03/23/89)
FORTRAN Dhrystone for i860? (2 replies, 03/23/89)
Architecture Simulation Tools summary (0 replies, 03/23/89)
gather/scatter hardware (2 replies, 03/23/89)
was: Don't look back. What about looking east? (6 replies, 03/24/89)
i860 overview (23 replies, 03/24/89)
U. Illinois Urbana-Champaign. (0 replies, 03/25/89)
How to make 2 workstations behave a (0 replies, 03/25/89)
PAWS (0 replies, 03/25/89)
undoing autoincrement (5 replies, 03/25/89)
physical vs. virtual cache (2 replies, 03/25/89)
PMAX/DS3100 frame buffers (5 replies, 03/25/89)
386 Unix & FP chips (0 replies, 03/26/89)
delay lines for memory (7 replies, 03/27/89)
>>>>> UPDATE: CS / EE / MATH Books for sale <<<<< (0 replies, 03/27/89)
foreign language requirements for PhDs (18 replies, 03/27/89)
EXACTLY what is Superscalar? (3 replies, 03/28/89)
What kinds of problems... (12 replies, 03/28/89)
Drum memory (4 replies, 03/28/89)
I/O for parallel computers - Summary (0 replies, 03/28/89)
Parallel I/O - bibliography (0 replies, 03/28/89)
Very Large Data Sets (0 replies, 03/28/89)
Interrupts (3 replies, 03/28/89)
How to use silicon (18 replies, 03/29/89)
XL series chips (0 replies, 03/29/89)
Structure member reorganizing (0 replies, 03/29/89)
mapping bothers physical i-cache? (0 replies, 03/29/89)
How does the i860 compare as a graphics (2 replies, 03/29/89)
How does the i860 compare as a (5 replies, 03/30/89)
ECL 88000 (4 replies, 03/30/89)
i860 cache flushing (5 replies, 03/30/89)
Sorting struct members for alig (0 replies, 03/30/89)
layering (0 replies, 03/31/89)
Unaligned Accesses (21 replies, 04/01/89)
Wired-OR in VLSI (0 replies, 04/01/89)
MACWORLD presents A real Macintosh Clone? (7 replies, 04/02/89)
Unaligned Accesses & comms. (0 replies, 04/02/89)
predicted yield of BIG microprocessors (3 replies, 04/02/89)
Call for votes: comp.realtime (0 replies, 04/02/89)
Unaligned data handling on PRISM (0 replies, 04/03/89)
finding Forth-83 (0 replies, 04/03/89)
1st annual Bay Area ACM/SIGGRAPH/Usenet Computer Graphics Ski meeting (0 replies, 04/03/89)
Time for a new topic: Sun-4/110 "SCRAM cache" and such (0 replies, 04/04/89)
RISC vs unaligned data (4 replies, 04/04/89)
Software implementing Quine-McCluskey algorithm (0 replies, 04/04/89)
SUN procedure inlining - Dhrystone numbers (0 replies, 04/05/89)
Hypercube routing (0 replies, 04/05/89)
Pearls of Wisdom (0 replies, 04/05/89)
UK Company Announces i860 Products (0 replies, 04/05/89)
FORTRAN Dhrystone for i860? [NO (2 replies, 04/06/89)
Query about miserable M68882 performance [really 80-bit not (0 replies, 04/06/89)
Sorting struct members for alignment (9 replies, 04/06/89)
SUN procedure inlining (9 replies, 04/06/89)
Query about miserable M68882 performance (3 replies, 04/06/89)
RISC as a "technology window"? (33 replies, 04/07/89)
predicted yield of BIG microprocess (3 replies, 04/07/89)
Parallel functional programming (1 reply, 04/08/89)
Myrias (0 replies, 04/08/89)
R/W Optical questions (1 reply, 04/08/89)
80-bit notes (3 replies, 04/08/89)
Query about miserable M68882 performance really 80-bit notes (4 replies, 04/09/89)
Livermore loops - 24 loop kernel version wanted (0 replies, 04/09/89)
foreign language requirements f (2 replies, 04/10/89)
looking for >32-bit address spa (1 reply, 04/11/89)
Journos... (0 replies, 04/11/89)
looking for >32-bit address space [and how will C handle it (3 replies, 04/11/89)
Async State Machines (0 replies, 04/12/89)
Segmentation (0 replies, 04/12/89)
Myrias system is real (0 replies, 04/12/89)
midway summary: the vote for comp.realtime (0 replies, 04/12/89)
looking for >32-bit address space (22 replies, 04/12/89)
Progress (1 reply, 04/12/89)
MicroVAX emulation (12 replies, 04/13/89)
address masking gimmick (1 reply, 04/13/89)
ARCHITECTURAL SIMULATOR (0 replies, 04/13/89)
Processor war ? 68040 and 80486 Bah ! (0 replies, 04/13/89)
Parallel Simulated Annealing / References and Are You Doing It? (0 replies, 04/14/89)
Unaligned data and old FORTRAN (8 replies, 04/15/89)
MIPS R2000 mul/div (0 replies, 04/16/89)
C pointers in longs (3 replies, 04/16/89)
to graphics processor or not to gra (0 replies, 04/16/89)
ICS 89 Program (0 replies, 04/17/89)
68040 and 80486 (8 replies, 04/17/89)
20 Gflop NEC machine (3 replies, 04/18/89)
Uses for shared memory machines? (1 reply, 04/18/89)
Specifying int size in C (1 reply, 04/18/89)
The Stone Collection (0 replies, 04/18/89)
Lumena converter NEEDED BAD!!! (0 replies, 04/18/89)
to graphics processor or not to graphics processor (6 replies, 04/19/89)
Portable Frankenstone (0 replies, 04/19/89)
Fibre Optics (0 replies, 04/21/89)
DARPA supercomputer (11 replies, 04/21/89)
Control Data Closes ETA Systems, Inc. (4 replies, 04/21/89)
looking for >32-bit address space and how will C handle it (15 replies, 04/21/89)
Z80 has no interruptible instructions (0 replies, 04/21/89)
RT/PC Unaligned Accesses (11 replies, 04/22/89)
ARM 'problems' (0 replies, 04/22/89)
Oh, not again! Re: DARPA supercomputer (2 replies, 04/22/89)
Core Memory (1 reply, 04/22/89)
CDC 8600 (6 replies, 04/23/89)
In search on the next generation standard bus (1 reply, 04/24/89)
nothing new (0 replies, 04/25/89)
Open coding (2 replies, 04/25/89)
Sustained Performance Computer Architecture (2 replies, 04/27/89)
What is IEEE *854* (0 replies, 04/27/89)
Needed : Hardware documentation for SUN 100U/150U (0 replies, 04/28/89)
System size (1 reply, 04/28/89)
Independent Architecture Complilers (7 replies, 04/28/89)
critical path of FP chips (1 reply, 04/28/89)
Voting period concluded for comp.re (0 replies, 04/28/89)
Metastability (6 replies, 04/29/89)
Connection Machine Summer Institute (0 replies, 04/29/89)
complexity (2 replies, 04/29/89)
Things compilers never need (3 replies, 04/29/89)
One aspect of bandwidth (18 replies, 04/30/89)
Dhrystone 2.n Results (29 replies, 05/01/89)
Connecting chips (1 reply, 05/01/89)
Run time code linking (0 replies, 05/01/89)
Optical computing reference (4 replies, 05/01/89)
486 and 68040 (14 replies, 05/02/89)
SoftEng or CS Graduate Program Search (0 replies, 05/02/89)
More on the Sustained Performance Architecture (0 replies, 05/03/89)
Generalizing Integers (0 replies, 05/03/89)
Architectural/Behavioral Simulator (0 replies, 05/03/89)
Cray - XMP article summary (0 replies, 05/03/89)
incremental compilation and code as data (1 reply, 05/03/89)
CDC 205 et al (6 replies, 05/04/89)
Register Window Size vs Language (0 replies, 05/04/89)
The IPI fast peripheral interface (8 replies, 05/04/89)
Virtualizable RISC Instruction Sets, and documentation (0 replies, 05/04/89)
architectural support in languages (0 replies, 05/05/89)
Rumors of death of 29K exaggerated? (5 replies, 05/05/89)
Speed (2 replies, 05/05/89)
Do you have bandwidth? (13 replies, 05/06/89)
Virtualizable RISC Instruction Sets (3 replies, 05/07/89)
Bandwidth and RISC vs. CISCOM (2 replies, 05/08/89)
WISC vs. RISC (0 replies, 05/08/89)
HICSS Minitrack on Exp. Research on Comp. Arch. (0 replies, 05/08/89)
WISC (5 replies, 05/08/89)
SONAR help and references needed (0 replies, 05/08/89)
SISC (6 replies, 05/09/89)
Bandwidth and RISC vs. CISC (37 replies, 05/09/89)
88K vs. MIPS vs. SPARC vs. 386 (9 replies, 05/09/89)
RISC and emulated languages (10 replies, 05/10/89)
Voting period concluded for comp.realtime (1 reply, 05/10/89)
Complex Instructions (47 replies, 05/10/89)
applications software (0 replies, 05/10/89)
What is IEEE *854* ? (0 replies, 05/11/89)
Re semaphores and ARM (0 replies, 05/11/89)
Sub groups ? (0 replies, 05/12/89)
Need information about 386 performance (1 reply, 05/12/89)
Object Translator (8 replies, 05/12/89)
MHZ/VUPs (0 replies, 05/12/89)
Message queues (9 replies, 05/12/89)
Semaphores (3 replies, 05/12/89)
Hottest Workstation for the money (3 replies, 05/13/89)
N-6 anyone ? (0 replies, 05/13/89)
WISC "impossibility" (4 replies, 05/14/89)
A little bit of data on register usage... (0 replies, 05/14/89)
should comp.arch be split (4 replies, 05/15/89)
microprocessor 2nd-level cache protocols for multiprocessing (0 replies, 05/15/89)
Content of comp.arch (0 replies, 05/15/89)
Intel-Bashing (3 replies, 05/15/89)
Interested in memory bandwidth figures for DEC PMAX & Sparcstation 1 (0 replies, 05/16/89)
unconventional architectures (13 replies, 05/16/89)
DG workstation (2 replies, 05/16/89)
Query about distributed memory machines (0 replies, 05/17/89)
Let's split comp.arch! (0 replies, 05/17/89)
Understanding variations in Dhrysto (0 replies, 05/17/89)
Retraction (0 replies, 05/17/89)
SPUR architecture: anything on it lately? (0 replies, 05/17/89)
wrongheadedness (0 replies, 05/17/89)
Cad system needed (0 replies, 05/18/89)
non-volatile RAMS --> FRAMS (1 reply, 05/18/89)
Questions on SparcStation 1 performance (8 replies, 05/18/89)
MIPS Magazine articles found (4 replies, 05/18/89)
Nsieve Results (3 replies, 05/18/89)
Purchasing Agents and Pontiffs (1 reply, 05/18/89)
file systems (0 replies, 05/18/89)
microprocessor 2nd-level cache protocols for multiprocessin (2 replies, 05/18/89)
Criteria for comparing RISC processors (28 replies, 05/18/89)
AT bus & disks (0 replies, 05/19/89)
370 conventions (2 replies, 05/19/89)
Understanding variations in Dhrystone performance (6 replies, 05/19/89)
New Generic Bus Architecture (0 replies, 05/19/89)
Silicon Innovation - was Re: Purchasing Agents and Pontiffs (1 reply, 05/19/89)
Simple query about Cray-2 architecture (1 reply, 05/19/89)
Looking for detailed documentation on a workstation (1 reply, 05/19/89)
80486 vs. 68040 code size (53 replies, 05/19/89)
Is anyone out there using Xilinx chips? (0 replies, 05/20/89)
thriving with your past (0 replies, 05/20/89)
Register Scoreboarding (22 replies, 05/20/89)
Questions on SparcStation 1 perform (0 replies, 05/21/89)
Criteria ... [really: are N des (3 replies, 05/21/89)
Q-M tunneling limitations on feature size ? (2 replies, 05/22/89)
68020 vs. 68030 speed (10 replies, 05/22/89)
POSITION AVAILABLE AT ECRC MUNICH (0 replies, 05/22/89)
Scoreboarding HW is simple (1 reply, 05/22/89)
special issue of CAN/call for papers (0 replies, 05/23/89)
DEDs SEDs WOMs & Disaster: Oh... I always thought black was GND (0 replies, 05/23/89)
World War III in RISC-land (0 replies, 05/23/89)
Multiport Micro Memories (4 replies, 05/23/89)
just when you thought it was safe to read (0 replies, 05/23/89)
WOM (3 replies, 05/24/89)
looking for RISCs (0 replies, 05/24/89)
Recovery Blocks (0 replies, 05/24/89)
Dynamic frequency analysis (4 replies, 05/24/89)
MMUs and operating systems (1 reply, 05/25/89)
286 segments and C (0 replies, 05/25/89)
Request for SPARC information sources (1 reply, 05/25/89)
88k info wanted (0 replies, 05/25/89)
California & Texas slug it out (3 replies, 05/25/89)
resume' amazements (1 reply, 05/25/89)
DTACK Grounded (2 replies, 05/27/89)
SUN 4/330 vs. DEC3100 (0 replies, 05/27/89)
tree-growing mesh (0 replies, 05/27/89)
When is a 68020 faster than a MIPS R2000? (0 replies, 05/27/89)
MMUs, Page Size, Resume Humor (1 reply, 05/28/89)
Interconnect strategies (0 replies, 05/29/89)
TISC processor (1 reply, 05/29/89)
Call For Discussion - proposal to create comp.sys.mips (3 replies, 05/29/89)
Multiple Insstruction Issue & Low-Level Parallelism (2 replies, 05/30/89)
High Level CPU Architectures (2 replies, 05/30/89)
When is a RISC not a RISC {was Scoreboarding HW is simple} (2 replies, 05/30/89)
are N designs better than 1? (24 replies, 05/31/89)
IEEE 754 vs. 854 (6 replies, 05/31/89)
ESD protection (4 replies, 05/31/89)
Criteria ... (1 reply, 06/01/89)
Criteria ... [really: are N designs (1 reply, 06/01/89)
80486 vs. 68040 code size [real (4 replies, 06/01/89)
Real-time flavours (0 replies, 06/02/89)
ESD protection on CHIPS (1 reply, 06/02/89)
Programming (4 replies, 06/02/89)
RISC vs CISC again (0 replies, 06/02/89)
comp.sys.mips (0 replies, 06/03/89)
8086 design goals (10 replies, 06/03/89)
Neurological Topology (2 replies, 06/03/89)
how many regs (31 replies, 06/04/89)
Writable instruction set cpus (1 reply, 06/05/89)
Real Time Oranges (0 replies, 06/05/89)
performance-sapping OSes (1 reply, 06/05/89)
Time Sync in MP System (2 replies, 06/05/89)
New Barrel Processor Work (3 replies, 06/06/89)
E2000 (15 replies, 06/07/89)
a silly VME bus question (6 replies, 06/07/89)
cray frontends... (0 replies, 06/08/89)
choosing Intel (0 replies, 06/08/89)
Responses to Distributed Memory Multiprocessor Query (0 replies, 06/08/89)
Apollo 10,000 R.I.P. (2 replies, 06/08/89)
Apollo 10,000 (0 replies, 06/09/89)
Apollo DN10000 *not* R.I.P. (0 replies, 06/09/89)
88000 implementations: ECL vs CMOS (1 reply, 06/09/89)
Mainframe Architectures (1 reply, 06/09/89)
Intel RISC 80960 (0 replies, 06/09/89)
superscalar (6 replies, 06/09/89)
Slandering Intel (13 replies, 06/09/89)
VAX Architecture (5 replies, 06/10/89)
fast memories (6 replies, 06/10/89)
Crays aren't cheap (0 replies, 06/10/89)
FeRAMs?? (1 reply, 06/10/89)
Register usage (48 replies, 06/10/89)
E2000 vs 68040 (1 reply, 06/10/89)
VHDL Simulator (1 reply, 06/10/89)
Register usage and Policy vs. Mechanism (0 replies, 06/11/89)
front ends to crays... (7 replies, 06/12/89)
DMA on RISC-based systems (40 replies, 06/12/89)
Why did Intel do it this way? (1 reply, 06/12/89)
Batter superlatives (1 reply, 06/13/89)
What is a ...-computer (4 replies, 06/13/89)
Divide by three? (13 replies, 06/13/89)
CALL FOR VOTES -- proposal to create comp.sys.mips (0 replies, 06/13/89)
Reserved register frames for interrupts (0 replies, 06/14/89)
Workstations for Lisp (6 replies, 06/14/89)
Self Modifying Code (7 replies, 06/15/89)
Hot Chips Symposium (2 replies, 06/15/89)
Call For Papers FTCS-20 (0 replies, 06/15/89)
4/330 write buffer (0 replies, 06/16/89)
Job in Performance Analysis (0 replies, 06/16/89)
RISC list (7 replies, 06/16/89)
TRON overview (0 replies, 06/17/89)
Another Mainframe question... (0 replies, 06/19/89)
Has anybody used SES/workbench, Network II.5, or COMMNET II.5 (0 replies, 06/20/89)
computer architecture: text recommendation? (0 replies, 06/20/89)
FRAM (8 replies, 06/21/89)
Coroutine switching (0 replies, 06/21/89)
DECStation vs. SPARCstation, need help! (6 replies, 06/21/89)
Dataflow architectures and Ray Tracing (0 replies, 06/21/89)
i860 Specmanship (0 replies, 06/21/89)
BBN Butterfly (3 replies, 06/22/89)
68000 architecture (11 replies, 06/22/89)
DS3100 floating point (0 replies, 06/23/89)
Simple disk benchmark results (9 replies, 06/24/89)
Question about IEEE floats (2 replies, 06/25/89)
Write-thru vs. Write-back caches (1 reply, 06/25/89)
anyone have comp.arch archived? (0 replies, 06/27/89)
Help on Weitek Chips (0 replies, 06/27/89)
i82786 R.I.P. ? (5 replies, 06/27/89)
Cadmus/Cambridge-Digital QBus MC68010 (3 replies, 06/27/89)
80186 Interrupts: Am I missing something? (1 reply, 06/28/89)
Info on Tektronix XD88 (0 replies, 06/28/89)
BIT SPARC (0 replies, 06/29/89)
Shadowing Video RAM (0 replies, 06/29/89)
parallel pipelines (1 reply, 06/30/89)
DSP56001 query (6 replies, 06/30/89)
Slandering Project MAC (3 replies, 06/30/89)
SPEC Bench-a-Thon (22 replies, 06/30/89)
MIPS, SPARK, RISC, and CISC (2 replies, 06/30/89)
HOT CHIPS conference (4 replies, 07/01/89)
ISA Development Survey (0 replies, 07/01/89)
MIPS Assembler Procedure (10 replies, 07/01/89)
Vectorized double length multiplication and division (0 replies, 07/04/89)
MIPS/MFLOPS ratio (8 replies, 07/05/89)
Universities in Britain (0 replies, 07/06/89)
TRON a little background - short form (0 replies, 07/06/89)
Dhrystone Benchmark Results (0 replies, 07/06/89)
What should be in a Progr.-Language (0 replies, 07/07/89)
VLIW assembly (0 replies, 07/07/89)
Micro-pipeline paper (0 replies, 07/08/89)
TRON Hammerlock?? (1 reply, 07/08/89)
User Interfaces (0 replies, 07/09/89)
Programming and Machine Operations (2 replies, 07/09/89)
Design philosophy (1 reply, 07/10/89)
Functions returning "list" of values (0 replies, 07/11/89)
MIPS/MFLOPS ratio long; here we go again; sorry (6 replies, 07/11/89)
Number of registers, windows (0 replies, 07/11/89)
paired registers (0 replies, 07/11/89)
Stop him before he KILLS AGAIN! (4 replies, 07/12/89)
intel 860 and its applications (0 replies, 07/12/89)
IEEE p854 (2 replies, 07/12/89)
Irrelevant postings... (0 replies, 07/13/89)
More RISC vs. CISC wars (12 replies, 07/14/89)
Re^2: TRON (0 replies, 07/14/89)
Ferroelectric RAMs (0 replies, 07/14/89)
Multiple Return Values From Functions (0 replies, 07/14/89)
More SPARC floating point (1 reply, 07/15/89)
Book on MIPS R3000? (2 replies, 07/17/89)
What's a multiprocessor, smirk (1 reply, 07/17/89)
DECSystem 20 Nostalgia (0 replies, 07/17/89)
CALL FOR DISCUSSION: comp.std.tron (0 replies, 07/18/89)
R2000/R3000 MIPS book (0 replies, 07/18/89)
manuals (0 replies, 07/18/89)
More math... (4 replies, 07/18/89)
long instructions & page faults (2 replies, 07/19/89)
References needed (0 replies, 07/19/89)
Object-oriented chip from BiiN. (2 replies, 07/19/89)
Publicly Available Math Library - FPSMath (0 replies, 07/20/89)
Register pairing (3 replies, 07/20/89)
Hardware Trophy Hunting (3 replies, 07/21/89)
iAPX-432 ? (3 replies, 07/21/89)
Bubble memories (0 replies, 07/21/89)
Need 50Mflops on a VME board (2 replies, 07/21/89)
Parallel Computer Options (0 replies, 07/21/89)
Announcement of Forthcoming NeXT Book (0 replies, 07/21/89)
long = short*short ; (0 replies, 07/22/89)
Optical Crossbars (0 replies, 07/22/89)
AT&T 3B20D (5 replies, 07/22/89)
Lightweight Tasks (0 replies, 07/22/89)
Microprocessor Forum (0 replies, 07/22/89)
Div/mod is a slow way to convert binary to decimal (0 replies, 07/22/89)
386/486 Virtual Memory Question... (15 replies, 07/22/89)
Language Tenets (7 replies, 07/22/89)
Double Width Integer Multiplication and Division (31 replies, 07/22/89)
Compiling - RISC vs. CISC (34 replies, 07/23/89)
Code scheduling (0 replies, 07/24/89)
Questions on segments and tagged architecture (2 replies, 07/25/89)
88k needs fewer instructions than VAX. (5 replies, 07/25/89)
Cost of RISC vs. CISC (0 replies, 07/26/89)
RISC is NOT micro-code (23 replies, 07/26/89)
IEEE floating point format (0 replies, 07/26/89)
Multiuser benchmarks (2 replies, 07/26/89)
PDP-1 tricks (0 replies, 07/26/89)
PDP-11 tricks (0 replies, 07/26/89)
Editor & System Performance (1 reply, 07/26/89)
divrem- what's the problem? (0 replies, 07/27/89)
autodecrement PC (2 replies, 07/27/89)
MIPS (0 replies, 07/27/89)
Making Rounding Modes Usable - We've Done That! (3 replies, 07/28/89)
Registers in memory (2 replies, 07/29/89)
WANTED: references to capabability machines (0 replies, 07/31/89)
SPARC address-valid times (0 replies, 07/31/89)
Why 36 bits. (2 replies, 08/01/89)
320C30 FFT timing (0 replies, 08/01/89)
another fun PDP-10 instruction (0 replies, 08/02/89)
Info on DSP chips (8 replies, 08/02/89)
Research Positions (0 replies, 08/02/89)
Cypress SPARC FPU question (0 replies, 08/03/89)
FPU chip set (7 replies, 08/03/89)
SPARC Implementations (4 replies, 08/03/89)
DECSYSTEM 20 (36 replies, 08/03/89)
IEEE Computer Special Issue (0 replies, 08/04/89)
Info requested on VHDL sub-committees (0 replies, 08/04/89)
i860 floating-point (3 replies, 08/05/89)
GaAs CPUs (0 replies, 08/05/89)
RISCs Register sets and PDP 10/20s (8 replies, 08/05/89)
Flash! 16 not power of 2! (2 replies, 08/08/89)
Flash! 16 not power of 2! really, CISC-to-the-max (2 replies, 08/08/89)
What is a Mainframe? (80 replies, 08/08/89)
HP Precision Architecture and Hitachi (1 reply, 08/08/89)
Flash! 16 not power of 2! really, registers in RAM (0 replies, 08/08/89)
World of Wonder (0 replies, 08/08/89)
PDP9 - what's it good for? (4 replies, 08/09/89)
New Bell Award (3 replies, 08/09/89)
80268 bugs (1 reply, 08/09/89)
Connection Machine (8 replies, 08/09/89)
MIMD on Connection Machine (1 reply, 08/10/89)
Length of single-precision FORTRAN floating point on Univac 1108/1109 (0 replies, 08/10/89)
Vector Machines? (2 replies, 08/11/89)
Literature list wanted:TRON,MAP,Bitbus (1 reply, 08/11/89)
Performance & Diagnosis (0 replies, 08/11/89)
DEC MASSBUS (3 replies, 08/13/89)
CISC Microprocessors (12 replies, 08/13/89)
DECsystem-20 (9 replies, 08/13/89)
All right, 16 is a power of 2 (0 replies, 08/14/89)
System reincarnation is bad security (0 replies, 08/15/89)
Patents on Microchannel (5 replies, 08/15/89)
Request information on Harris machine (2 replies, 08/15/89)
TLB traffic reports (1 reply, 08/16/89)
Lights (3 replies, 08/17/89)
Cache controller info wanted (0 replies, 08/17/89)
Memory Models (0 replies, 08/17/89)
Was: delayed branch Now: Weitek XL (0 replies, 08/17/89)
Context-switch times (1 reply, 08/17/89)
Double precision calculation with 88000 (0 replies, 08/18/89)
Cycle Counter (10 replies, 08/18/89)
New TI DSP chip (4 replies, 08/18/89)
looking for reference to Livermore Loops benchmark (0 replies, 08/20/89)
Papers on caching strategys wanted (4 replies, 08/20/89)
really, CISC-to-the-max (4 replies, 08/21/89)
Making Rounding Modes Usable (6 replies, 08/21/89)
Why 32 bits? (3 replies, 08/21/89)
Multiply & Divide (0 replies, 08/22/89)
fast square root (0 replies, 08/22/89)
Observability (1 reply, 08/23/89)
Correction of quote (0 replies, 08/23/89)
What is a Transputer? (0 replies, 08/24/89)
rekursiv (0 replies, 08/24/89)
John von Neumann, sqrt instr (12 replies, 08/24/89)
cache speed (10 replies, 08/24/89)
How do you collect instruction traces? (0 replies, 08/25/89)
Superscalar ISAs (2 replies, 08/25/89)
REKURSIV object-oriented architecture (2 replies, 08/25/89)
Disk cache general strategies? (0 replies, 08/25/89)
dineroIII (2 replies, 08/25/89)
Am29000 simulator (0 replies, 08/25/89)
more Observability (6 replies, 08/25/89)
Vectorizing division in a do loop (4 replies, 08/25/89)
IPI-2 vs. SCSI (2 replies, 08/26/89)
PCB technology parameters wanted (0 replies, 08/28/89)
Forced to use TRON (2 replies, 08/28/89)
VM Hardware (0 replies, 08/28/89)
hardware complex arithmetic support (16 replies, 08/29/89)
Working Set replacement, use bits (1 reply, 08/29/89)
Weitek XL (0 replies, 08/29/89)
disk striping (38 replies, 08/30/89)
VAX bashing and language specificity of processors (2 replies, 08/30/89)
"special purpose" hardware (0 replies, 08/31/89)
Instruction continuation funnies (0 replies, 08/31/89)
Memory utilization & inter-process (10 replies, 08/31/89)
Who knows better: you or the OS? (0 replies, 08/31/89)
What is a coprocessor... and is the i860 one? (0 replies, 08/31/89)
delayed branch (32 replies, 08/31/89)
Block Floating point. (0 replies, 09/01/89)
another PDP-10 benefit to Lisp (0 replies, 09/01/89)
Blitter+VRAM chips (0 replies, 09/01/89)
Locking barn doors [Was RE: Parity hdw for uninit var checking? (0 replies, 09/02/89)
Lisp Chips (2 replies, 09/02/89)
Memory utilization & inter-process contentionREAD/NEW/FOLLOWUP (0 replies, 09/02/89)
SCSI on steroids, mainframes move over (14 replies, 09/02/89)
fast DRAMs and caches (8 replies, 09/03/89)
Memory utilization (0 replies, 09/03/89)
Claimed bug in 80286 (15 replies, 09/03/89)
Lisp machines (0 replies, 09/04/89)
29000/960/680?0/88000 (0 replies, 09/05/89)
What is a coprocessor? ... and is the i860 one? (2 replies, 09/06/89)
UPDATE + PROPOSAL + CALL FOR VOTES: comp.dsp (0 replies, 09/06/89)
286/386 undocumented instruction (0 replies, 09/06/89)
NS32GX32 for realtime (0 replies, 09/07/89)
Parity hardware for uninitialized variable checking? (8 replies, 09/07/89)
TRON: call for votes will not proceed (0 replies, 09/08/89)
Synchronizer failure; MTBF (2 replies, 09/08/89)
DMCC5 Call For Participation (0 replies, 09/08/89)
Massive Parallelism Workshop - Program (0 replies, 09/08/89)
Was: Memory utilization & inter-process contention (0 replies, 09/08/89)
Summary of Multiprocessor Hunt (2 replies, 09/09/89)
forced declare-time initialization considered useless (0 replies, 09/12/89)
Memory utilization & inter-process contention (60 replies, 09/12/89)
Computer architecture project (0 replies, 09/12/89)
Book on Fault Tolerance Wanted (0 replies, 09/12/89)
Parity in Internal Data Paths of Pr (0 replies, 09/12/89)
VAX appreciation society (0 replies, 09/13/89)
RISC and languauges (2 replies, 09/13/89)
Scheduler for scalar/vector machine (0 replies, 09/13/89)
DMA and SCSI, Synchronous and not (0 replies, 09/13/89)
Instruction Restart and I/O (2 replies, 09/14/89)
29K (1 reply, 09/14/89)
AT DMA arch.; Was: Re: DMA and SCSI, Synchronous and not (0 replies, 09/14/89)
the meaning of "memory-locked" (0 replies, 09/15/89)
How Caches Work (23 replies, 09/15/89)
uninitialized variable checking (3 replies, 09/15/89)
Parity in Internal Data Paths of Processors (9 replies, 09/15/89)
Arbiter / Synchronizer failure; MTBF (0 replies, 09/15/89)
SRAM vs. DRAM, 33MHz 386 UNIX-PC (22 replies, 09/16/89)
Press Release: Intel's i960 CA Superscalar Microprocessor (0 replies, 09/16/89)
References wanted on RISC architectures. (1 reply, 09/16/89)
I/O and disks (0 replies, 09/16/89)
25th Anniversary of 36 Bits (5 replies, 09/16/89)
PC vs. mainframe I/O (8 replies, 09/18/89)
Crystal oscillator theory. (4 replies, 09/18/89)
EISA bus future (0 replies, 09/18/89)
Chaotic motion in caches (0 replies, 09/19/89)
NACLP'89 Architecture Workshop (0 replies, 09/19/89)
pipelining (1 reply, 09/19/89)
flexible caches (9 replies, 09/19/89)
DISC (3 replies, 09/19/89)
Filling branch delay slot with test (9 replies, 09/19/89)
Adaptec SCSI chip (0 replies, 09/21/89)
Raytracer performance on machines? (1 reply, 09/22/89)
Fast conversions, another urban myt (0 replies, 09/22/89)
Help with 68020/68881 Stack problem (0 replies, 09/23/89)
Harris RTX, Hitachi AI32 info needed (1 reply, 09/24/89)
more soap box (5 replies, 09/24/89)
Differentiation and Compatibility (3 replies, 09/24/89)
COBOL Decimal Arithmetic (3 replies, 09/25/89)
Gnu assembler for the 80860, linker info needeed (0 replies, 09/25/89)
Please edit the Subject: line! (0 replies, 09/26/89)
Numbers (7 replies, 09/26/89)
DSP chip future questions (0 replies, 09/26/89)
Bandwidth Wasters Hall of Fame (1 reply, 09/26/89)
Need info on SPARC & MIPS (0 replies, 09/28/89)
PL.8 internals (2 replies, 09/28/89)
Data Vault (0 replies, 09/28/89)
Bandwidth Wasters Hall of Fame for comp.arch (13 replies, 09/29/89)
More on books (1 reply, 09/29/89)
Books to read before thinking about computer architecture (6 replies, 09/29/89)
VLIW Architecture - References, other projects (0 replies, 09/29/89)
Application specific benchmarking (2 replies, 09/30/89)
"Your Lights Are On.." (0 replies, 09/30/89)
fast I/O=less waiting time (0 replies, 10/02/89)
Variable Page size (6 replies, 10/02/89)
LEGOs -- and Tinker-Toys (1 reply, 10/02/89)
88000 vs 3081. (5 replies, 10/02/89)
Pipeline Interlock (1 reply, 10/03/89)
IEEE FP denorms and Deming's Arithmetics With Variable Precision (3 replies, 10/04/89)
*big iron*, io bandwidth (0 replies, 10/04/89)
Asynchronous cpu, self-timed cirtuits. (0 replies, 10/05/89)
RISC information wanted (0 replies, 10/05/89)
programming the com port (3 replies, 10/05/89)
MIDI on the PC (3 replies, 10/06/89)
Asynchronous cpu (6 replies, 10/06/89)
Research on Memory Systems and Autom. Garbage Collection ?? (0 replies, 10/06/89)
Fast conversions, another urban (2 replies, 10/06/89)
Bad Tidings? (4 replies, 10/07/89)
Rubin debate (0 replies, 10/07/89)
FPS 64 bit products (0 replies, 10/08/89)
data-flow architecture (0 replies, 10/09/89)
LEGOs -- computationally complete? (12 replies, 10/10/89)
shared memory vs. bus master DMA on AT Bus (0 replies, 10/10/89)
Instruction (59 replies, 10/10/89)
*big iron* (31 replies, 10/10/89)
binary isn't faster (0 replies, 10/11/89)
desperately seeking explanation of typical SCSI configuration (2 replies, 10/11/89)
integer alignment problems on RT (10 replies, 10/12/89)
Associative/Content Addressable memories & processors (0 replies, 10/12/89)
Minimizing microcode (1 reply, 10/13/89)
How to get the HP Journal (0 replies, 10/13/89)
VLIW Architecture (32 replies, 10/13/89)
Graphics coprocessors (2 replies, 10/13/89)
ISP (0 replies, 10/14/89)
RISCs and real-time operating systems (0 replies, 10/15/89)
Am looking for any info about optimizing Ada via Hardware (0 replies, 10/15/89)
Self-modifying codeREAD/NEW/FOLLOWUP (0 replies, 10/15/89)
Micro 2000 (3 replies, 10/15/89)
Result of RT integer alignment problem / other CPU's (1 reply, 10/16/89)
Simulation of scalable shared memory architectures (0 replies, 10/16/89)
Fast conversions, another urban myth? (31 replies, 10/16/89)
Self-modifying CP/M code (0 replies, 10/16/89)
Re : Graphics coprocessors (3 replies, 10/16/89)
VLIW SPECmarks (1 reply, 10/17/89)
Wanted: Benchmarks for Array/Matrix Processors (0 replies, 10/17/89)
Request for DSP Code. (0 replies, 10/17/89)
CAM circuit information request (0 replies, 10/17/89)
test and set facility (4 replies, 10/17/89)
DSP code requested (0 replies, 10/17/89)
Japanese Fifth Generation Supercomputer Killer (0 replies, 10/17/89)
Virtual Machine Network Decription Syntaxes (0 replies, 10/18/89)
Computer Architecture and Networks (1 reply, 10/18/89)
data-flow (1 reply, 10/19/89)
Impossible DRAMs (0 replies, 10/19/89)
1Meg DRAM supply voltage (4 replies, 10/19/89)
IBM Workstations (4 replies, 10/20/89)
Microsoft and faster machines (2 replies, 10/20/89)
UCB Publications (0 replies, 10/20/89)
break on data reference, was Re: More mips (1 reply, 10/20/89)
PC Industry (0 replies, 10/20/89)
the IBM 801, was ERISC??? (0 replies, 10/20/89)
linpack (6 replies, 10/21/89)
call for discussion: comp.lang.specification (0 replies, 10/21/89)
Evil Canadian Twit From Hell (0 replies, 10/21/89)
Functional Languages (0 replies, 10/22/89)
Dasgupta: What isn't RISC (1 reply, 10/22/89)
parallel systems vs. uni-processors (4 replies, 10/22/89)
dataflow recent refs request (1 reply, 10/23/89)
HELP! Nasty Analogue Things (0 replies, 10/23/89)
VLIW Architecture - References, oth (9 replies, 10/23/89)
More mips (4 replies, 10/24/89)
AS/400 info (0 replies, 10/24/89)
Jack Dongarra's report (0 replies, 10/24/89)
Gate delays in fast computers (5 replies, 10/24/89)
Transient faults in memories (1 reply, 10/24/89)
Supercomputers (0 replies, 10/24/89)
Mips, Mach, test-and-set (7 replies, 10/25/89)
Gigabytes (0 replies, 10/25/89)
64Kb RAMs cannot be done with optical processes (1 reply, 10/25/89)
Location of netlib (0 replies, 10/26/89)
TRON Symposium (1 reply, 10/26/89)
was Self-modifying code (0 replies, 10/26/89)
Needs of Clerical Users. (2 replies, 10/26/89)
parallel systems (25 replies, 10/26/89)
parallel systems vs. uni-proces (1 reply, 10/26/89)
break on data reference (1 reply, 10/27/89)
Re^2: ATTACK OF KILLER MICROS (1 reply, 10/27/89)
Shared Memory vs. Distributed Systems (4 replies, 10/27/89)
Lamport's Baker's algorithm. (0 replies, 10/27/89)
PC hardware (0 replies, 10/27/89)
Trends (1 reply, 10/27/89)
1000000x1000000 Matrix (8 replies, 10/28/89)
What is specmarks?? (0 replies, 10/29/89)
64Kb RAMs cannot be done with optic (1 reply, 10/29/89)
i960CA (1 reply, 10/30/89)
Lisp machine architectures in retrospect (1 reply, 10/31/89)
Cray divide speed (1 reply, 10/31/89)
On-chip/ Off-chip Cache (0 replies, 10/31/89)
3010 fp (4 replies, 10/31/89)
Need benchmark C source code (0 replies, 11/03/89)
Compaq finds problem with chip (1 reply, 11/04/89)
Compaq 486 + Weitek 4167 (0 replies, 11/09/89)
Workstation speed comparisons (0 replies, 11/09/89)
Memory-reference traces (0 replies, 11/09/89)
AMD 29000 - no (1 reply, 11/09/89)
Compiler optimization and RISC. (0 replies, 11/09/89)
GOTO considered essential?? (6 replies, 11/10/89)
Looking for Prolog Chip (1 reply, 11/10/89)
Wanted:LISP Machine Simulators and LISP Compiler Source (0 replies, 11/10/89)
trig function question (0 replies, 11/10/89)
Unsafe at any speed (1 reply, 11/10/89)
RPN Calculators (0 replies, 11/10/89)
comp.vlsi (0 replies, 11/11/89)
Learning envirorment for CS/EE undergrads in Organization (0 replies, 11/11/89)
multi-threaded SPARC question (0 replies, 11/11/89)
Using Intel's 80960 (0 replies, 11/11/89)
load-store architecture (0 replies, 11/12/89)
Dynamic parallelism (0 replies, 11/12/89)
MIPS Co's 55 MIPS machine (2 replies, 11/12/89)
EISA and MCA (0 replies, 11/12/89)
Compaq find problem with chip (16 replies, 11/12/89)
Fed up with MIPS (17 replies, 11/13/89)
Autoincrement and RISCs (0 replies, 11/13/89)
Modelling workshop (0 replies, 11/13/89)
Microprocessors: waste & utilization (0 replies, 11/14/89)
Alliant/Intel PAX parallel computing standard (3 replies, 11/14/89)
CISC/RISC sizes of logic/cache (0 replies, 11/14/89)
comp.nostalgia (0 replies, 11/15/89)
Need info on SPARC MMUs and Caches (0 replies, 11/15/89)
ERISC??? (18 replies, 11/15/89)
Self-modifying code (215 replies, 11/15/89)
What is a good SCSI controller? (0 replies, 11/15/89)
Memory in Everex?? (1 reply, 11/15/89)
Microprocessors: waste & utilizatio (0 replies, 11/16/89)
This is another test (0 replies, 11/16/89)
Bootstrapping, was Self-modifying code (2 replies, 11/16/89)
Software modularity vs. instruction locality (7 replies, 11/16/89)
multiplexing jobs on a fast cpu to hide memory latency (0 replies, 11/16/89)
computation bandwidth (1 reply, 11/17/89)
Seeking references on concurrency control & recovery mechanisms (0 replies, 11/17/89)
80-20 (10 replies, 11/17/89)
Parallel project (0 replies, 11/17/89)
DVI and the i750 (0 replies, 11/17/89)
SCSI drive performance (0 replies, 11/18/89)
ENIAC Query (9 replies, 11/18/89)
Quantum Dynamics saving the Super Computers (1 reply, 11/18/89)
Multiple coprocessors? (1 reply, 11/18/89)
microcode (0 replies, 11/19/89)
Microelectronics/VLSI Design Opening at U.Patras (0 replies, 11/19/89)
Needed: Landmark, Norton SI, PC Bench 5 (0 replies, 11/20/89)
Surges (4 replies, 11/21/89)
BIT parts (0 replies, 11/21/89)
Multibus II <-> VME adapter? (1 reply, 11/21/89)
Digital rx01 floppy drives (0 replies, 11/21/89)
Needed: Linepack, Livermore loops (0 replies, 11/22/89)
ATTACK OF KILLER MICROS (83 replies, 11/22/89)
IIT coprocessor experience? (0 replies, 11/22/89)
ETA10 (4 replies, 11/23/89)
RISC multiprocessors (20 replies, 11/23/89)
Call for Papers - Summer 1990 USENIX, Anaheim, CA (0 replies, 11/23/89)
Slow SCSI (8 replies, 11/23/89)
neural net advice (0 replies, 11/24/89)
The Burst Computer (2 replies, 11/24/89)
Physical >= Virtual (1 reply, 11/26/89)
I/O processors (0 replies, 11/27/89)
Downsizing and K.M.'s (0 replies, 11/27/89)
High speed bus on the new MIPS R6000 box (5 replies, 11/27/89)
Evans and Sutherland quits the supe (0 replies, 11/27/89)
Back to the killer micro flames... sigh... (0 replies, 11/27/89)
Late, Lamented E&S-1 -- whats it look like? (6 replies, 11/28/89)
I/O, I/O, and off to work I go... (4 replies, 11/28/89)
Evans and Sutherland quits the superbusiness (14 replies, 11/28/89)
i960, i860, etc (4 replies, 11/28/89)
Killer Micros (6 replies, 11/28/89)
What CMOS cannot do (7 replies, 11/28/89)
R6000 vs BIT SPARC (5 replies, 11/29/89)
JIAWG benchmarks, R3000, i960CA (0 replies, 11/30/89)
AS/400 hardware architecture wanted (4 replies, 11/30/89)
Uses for unusual instructions (4 replies, 12/01/89)
GaAs considered a dead end (4 replies, 12/01/89)
Low cost NS32532 system (0 replies, 12/01/89)
Reliability Software (0 replies, 12/01/89)
NEED INFORMATION on GaAs (2 replies, 12/01/89)
The ATTACK OF THE KILLER MICROS (2 replies, 12/01/89)
NEED INFO ON i486 OR EISA (0 replies, 12/01/89)
MC68030 25MHz ICE Wanted (0 replies, 12/02/89)
VAX 9000 Vector Reduction (0 replies, 12/02/89)
Reply to Steve McGeady (0 replies, 12/02/89)
Are there archives for conp.arch? (0 replies, 12/02/89)
Are there archives for comp.arch? (1 reply, 12/02/89)
On chip caches (1 reply, 12/03/89)
NEC V80 (4 replies, 12/04/89)
AS/400 (0 replies, 12/04/89)
Prisma is gone (5 replies, 12/05/89)
"Private Eye": new cheap display technology (1 reply, 12/05/89)
Book Review (0 replies, 12/05/89)
design (0 replies, 12/05/89)
What are self-timed rams? (0 replies, 12/06/89)
Parallel Tools (0 replies, 12/06/89)
ICE for z8000 (0 replies, 12/06/89)
System clock rate vs. memory chip speed. (4 replies, 12/07/89)
couple more books on parallelism (0 replies, 12/07/89)
Politics and Architectures (3 replies, 12/07/89)
posix-testing mailing list created (0 replies, 12/08/89)
Number of 386 Transistors? (2 replies, 12/09/89)
Refs algorithms not requiring consistency (0 replies, 12/09/89)
suggested guidelines for references (0 replies, 12/09/89)
Synchronous versus Asynchronous SCSI (3 replies, 12/09/89)
Coherent cache for Killer Micros (5 replies, 12/10/89)
SPEC rating? (0 replies, 12/11/89)
comp.specification - second call for votes (0 replies, 12/12/89)
55 MIPS & 66 MIPS (20 replies, 12/12/89)
Galileo (0 replies, 12/12/89)
The new IBM RTs (0 replies, 12/13/89)
GaAs considered dead , indium phosphide, rod logic? (9 replies, 12/13/89)
Late Bloomers Revisited (0 replies, 12/13/89)
Amd/Xilinx LCA's (0 replies, 12/13/89)
R6000 FPU question (0 replies, 12/14/89)
UNIX and multiple CPUs (0 replies, 12/14/89)
Bus Arbitration (0 replies, 12/14/89)
Intel 860 Architecture (7 replies, 12/14/89)
Cyrix -- avoiding the I/O bottleneck (0 replies, 12/14/89)
Clock Rates (4 replies, 12/14/89)
ISSCC errata (1 reply, 12/14/89)
MPX (0 replies, 12/15/89)
Dhrystone (0 replies, 12/15/89)
pseudo-static RAM (2 replies, 12/15/89)
Cyrix - Fast Divide, etc. (7 replies, 12/15/89)
IEEE 754 "rem" query (1 reply, 12/15/89)
Differing clock rates in one system... (1 reply, 12/16/89)
Is there such a book? (3 replies, 12/16/89)
Reciprocal approximation (1 reply, 12/16/89)
Microprocessors (2 replies, 12/16/89)
That Damn Next Questionare! (0 replies, 12/18/89)
Pipelined FP add (8 replies, 12/18/89)
Myrias Programming Model (0 replies, 12/19/89)
MYRIAS - yet again (6 replies, 12/19/89)
X-terms v. PCs v. Workstations (29 replies, 12/19/89)
VME Bus Standard (20 replies, 12/19/89)
_really_ ciscy (4 replies, 12/20/89)
RISC bus (0 replies, 12/20/89)
Japanese Josephson breakthrough? I (0 replies, 12/20/89)
Home Bus (0 replies, 12/20/89)
The Art of Computer Architecture (5 replies, 12/21/89)
The Art of Floating Point (1 reply, 12/21/89)
In computing, late-bloomers are usually never-bloomers (6 replies, 12/22/89)
80960KA and KB (2 replies, 12/23/89)
MIPS R[23]000 and Kane's book (2 replies, 12/23/89)
OPTIMUL (0 replies, 12/23/89)
fad computing (13 replies, 12/26/89)
What Ever Happened To Big Shift Registers ??? (0 replies, 12/27/89)
Cellular Automata Processors (1 reply, 12/27/89)
Wait states on the 8051?? (0 replies, 12/28/89)
Japanese Josephson breakthrough? Implications? (9 replies, 12/28/89)
multi-user benchmark (0 replies, 12/29/89)
Limits of Computation (0 replies, 12/30/89)
fight over who agrees the most (1 reply, 12/31/89)
WOULD *YOU* BUY A NeXT COMPUTER? (8 replies, 01/01/90)
Marketing: The Final Frontier (0 replies, 01/01/90)
The Killer Micro From Hell [Rea (0 replies, 01/03/90)
X terminals / Workstations. (0 replies, 01/03/90)
register saving on MIPS csw (1 reply, 01/04/90)
Context switching on RISC chips (10 replies, 01/04/90)
Re^2: IBM PC prehistory (1 reply, 01/04/90)
Covert Channels (0 replies, 01/04/90)
info needed on optical disks (0 replies, 01/05/90)
Yearly request for suggested readings on parallel processing (0 replies, 01/05/90)
Apollo DN330's FOR SALE (0 replies, 01/06/90)
Memory Bandwidth vs. Processor Speed (2 replies, 01/06/90)
Integer Multiply/Divide (5 replies, 01/06/90)
Wanted: computer with fast context switching (0 replies, 01/08/90)
Integer/Multiply/Divide on Sparc (10 replies, 01/08/90)
KM's vs. Supers (2 replies, 01/09/90)
New benchmark (5 replies, 01/10/90)
Sanity Check, please (4 replies, 01/10/90)
uP technology, A.D. 2000 (0 replies, 01/10/90)
The Killer Micro From Hell [Really: fight ... (8 replies, 01/11/90)
New Moto FP chip (5 replies, 01/11/90)
Compilers and programming style (0 replies, 01/11/90)
Integer multiply and killer micros (7 replies, 01/11/90)
Re^2: Reasons why you don't prove your programs are correct (0 replies, 01/11/90)
solbourne series/5 questions... (0 replies, 01/11/90)
chip manufacturing (0 replies, 01/12/90)
Dhrystones (9 replies, 01/12/90)
SparcStations vs. Sun 3s! (0 replies, 01/12/90)
R6000 PCs? (11 replies, 01/13/90)
ABI vs. POSIX (0 replies, 01/13/90)
Message from God (0 replies, 01/13/90)
Reasons why you don't prove your programs are correct (9 replies, 01/13/90)
When's Next Dhrystone? (0 replies, 01/13/90)
Am7990 LANCE chip (1 reply, 01/13/90)
Program verification is a proven concept (0 replies, 01/14/90)
New buzzword (8 replies, 01/14/90)
LoadAll? (6 replies, 01/15/90)
The Killer Micro From Hell (20 replies, 01/15/90)
6000's Actually What computing power is needed? (0 replies, 01/16/90)
Here are five counterexamples (7 replies, 01/16/90)
R6000 PCs? no, but later CMOS ones (3 replies, 01/16/90)
IBM 9000 (0 replies, 01/16/90)
Wanted: Programs for Viterbi Decoder Algorithm (0 replies, 01/16/90)
Sun/Sparc FPUs (5 replies, 01/16/90)
New Intel mutliprocessor machine? (2 replies, 01/16/90)
Futurebus+ @ 500MBytes/sec (8 replies, 01/16/90)
Video Board -- need references (1 reply, 01/16/90)
US Memories Folds (0 replies, 01/16/90)
The trouble with fork (0 replies, 01/17/90)
Re^2: R6000 PCs? (0 replies, 01/17/90)
Fiber channels (8 replies, 01/17/90)
ABI and growth (6 replies, 01/17/90)
Multiprocessors and UNIX (0 replies, 01/17/90)
Error checking on ALU operations (0 replies, 01/18/90)
SPEC Solicits Benchmark Applications (0 replies, 01/18/90)
trapping FP instructions (0 replies, 01/18/90)
Are RISC programs bigger than C (0 replies, 01/18/90)
New benchmark results (0 replies, 01/18/90)
The Killer Micro From Hell actually, reliability (2 replies, 01/18/90)
loading (2 replies, 01/18/90)
68000 prehistory, was IBM PC prehistory (4 replies, 01/18/90)
Parity checking ALU's (0 replies, 01/18/90)
68K's & MMU's (1 reply, 01/18/90)
IBM PC prehistory (59 replies, 01/19/90)
Are RISC programs bigger than CISC? (5 replies, 01/19/90)
Cool CMOS at ECL speeds (5 replies, 01/19/90)
Reliability (5 replies, 01/19/90)
Why fork? (12 replies, 01/19/90)
386 pipelined addressing mode (1 reply, 01/20/90)
Workshops (0 replies, 01/22/90)
Has the 486 been fixed? Does AMI use it? (0 replies, 01/23/90)
Integer Multiply/Divide on Sparc (61 replies, 01/25/90)
Motorola DMA controllers (0 replies, 01/30/90)
SPARC & R2000 Exception Return (0 replies, 02/01/90)
Optical processor news info req... (0 replies, 02/01/90)
What is "V" ? (0 replies, 02/02/90)
Cache flush penalty at context switch. (1 reply, 02/02/90)
structures (2 replies, 02/02/90)
IBM 370 Operand Alignment (1 reply, 02/03/90)
What's new in multi-ported memories? (0 replies, 02/03/90)
Info about disk striping wanted (0 replies, 02/03/90)
Address Traces Wanted (0 replies, 02/05/90)
370 Operand Alignment and Page Faults (3 replies, 02/05/90)
Call for Papers, TAI90 Conference (0 replies, 02/06/90)
Fault Tolerant Micros (7 replies, 02/07/90)
80486A rumors? (0 replies, 02/07/90)
Futurebus+ overview (0 replies, 02/08/90)
AT&T/Bell Labs Optical Computer (1 reply, 02/08/90)
Number of Workstations out there (1 reply, 02/08/90)
Deja vu? Architecture book name? (4 replies, 02/08/90)
TRON (66 replies, 02/09/90)
Cyrix 83D87 Cheaper Than Intel's 387? Not really : (1 reply, 02/09/90)
Fault Tolerance LONG (4 replies, 02/09/90)
Clock Rate Efficiency (0 replies, 02/09/90)
Moore's Law (11 replies, 02/09/90)
88K vs. SPARC (0 replies, 02/09/90)
88k - what bug level? (2 replies, 02/10/90)
TRON's birthday (0 replies, 02/10/90)
the Multics from the black lagoon (0 replies, 02/11/90)
Scaling (0 replies, 02/11/90)
Time between memory failure (2 replies, 02/11/90)
i960 (0 replies, 02/11/90)
Benchamrks (0 replies, 02/12/90)
ROM speed (0 replies, 02/12/90)
MC68040 benchmark claims (1 reply, 02/12/90)
Multi-processor NeXT (1 reply, 02/13/90)
Drystone Benchmarks (0 replies, 02/13/90)
clock-rate lockstep (0 replies, 02/13/90)
Fault Tolerance (4 replies, 02/13/90)
big objects, 64-bit addresses, etc. (0 replies, 02/13/90)
Byte ordering (13 replies, 02/13/90)
Bus Partitioning? (7 replies, 02/13/90)
64 bit registers (3 replies, 02/13/90)
Next computer (47 replies, 02/13/90)
Binary<->Decimal conversion (0 replies, 02/13/90)
Latest SPECmarks (2 replies, 02/13/90)
SPECmark rating of MIPS RC6280? (0 replies, 02/14/90)
Compilers and RISC (5 replies, 02/14/90)
64/32 bit processors - impending disaster or time to grow? (0 replies, 02/14/90)
680x0 instructions (4 replies, 02/14/90)
Handling mis-alignment (4 replies, 02/14/90)
NeXT and Multics-bashing (7 replies, 02/14/90)
Multics & Memory mapped files (13 replies, 02/14/90)
Vector processor instruction sets (0 replies, 02/14/90)
Compilers vs. architecture (3 replies, 02/14/90)
64/32 bit processors - impending disaster? (4 replies, 02/14/90)
64-bit code addresses (0 replies, 02/14/90)
i860 regarded != "a 64-bit microprocessor" (0 replies, 02/14/90)
mmap (7 replies, 02/14/90)
the Multics from the black lago (2 replies, 02/14/90)
First Release of the AE Tracing System (0 replies, 02/15/90)
Apple Lisa? Multics? please!!! (0 replies, 02/17/90)
3-input operand instructions -- BITFIELDS, etc (0 replies, 02/20/90)
EISA bus spec wanted (0 replies, 02/21/90)
Structures' member order in C (0 replies, 02/21/90)
SPARC vs MC68040 (9 replies, 02/21/90)
Compiler writers vs. architects (0 replies, 02/21/90)
CISC Silent Spring (28 replies, 02/22/90)
"Small memory"? (0 replies, 02/22/90)
'040 vs. SPARC (15 replies, 02/22/90)
Supporting arbitrary precision arithmetic (0 replies, 02/22/90)
Evolutionary instruction sets (0 replies, 02/22/90)
Benchmarks (7 replies, 02/22/90)
88k MUL/DIV (1 reply, 02/22/90)
Acorn RISC Machine? (0 replies, 02/22/90)
Multics (1 reply, 02/23/90)
64-bit addresses and constant pools (0 replies, 02/23/90)
on IBM systems (0 replies, 02/23/90)
the Multics from the black lagoon :-) (28 replies, 02/23/90)
i860 (1 reply, 02/23/90)
Evolution towards super-scalar (0 replies, 02/23/90)
Paper tape vs card structuring (2 replies, 02/23/90)
Soft page tables (0 replies, 02/24/90)
disk latency (0 replies, 02/24/90)
hmmm, BitBlt, New Instructions For RISC (1 reply, 02/24/90)
Futurebus+ spec ordering info (0 replies, 02/24/90)
Risc System/6000 (0 replies, 02/24/90)
apologies (0 replies, 02/24/90)
RISC Machine Data Structure Word Alignment Problems? (38 replies, 02/24/90)
hmmm (2 replies, 02/24/90)
shared pages, was 64-bit addresses (0 replies, 02/24/90)
68040 (15 replies, 02/24/90)
Vector performance without vector instructions. (0 replies, 02/25/90)
A challenge -- C preprocessor expression for machine's `endian-ness'? (0 replies, 02/26/90)
IBM RISC system 6000 (0 replies, 02/26/90)
reg windows for 0-0 langs. (0 replies, 02/26/90)
Inverted Tables (0 replies, 02/26/90)
Lisa-IIx ? (8 replies, 02/26/90)
64-bit addresses & multiprocessor cache request (2 replies, 02/26/90)
Features for multiprecision arithmetic) (1 reply, 02/27/90)
HP-PA and MPE XL (1 reply, 02/27/90)
Error in Posting of SPEC numbers on IBM systems (4 replies, 02/27/90)
Question on multiprocessor bus/mem speed (1 reply, 02/27/90)
VAX 9000 tested at 57.28 VUPs (3 replies, 02/27/90)
IBM RISC System/6000 (0 replies, 02/27/90)
SPECmarks (25 replies, 02/28/90)
Parity (8 replies, 02/28/90)
bus on new IBMs (8 replies, 02/28/90)
HP-PA and MPE XL page architecture (1 reply, 02/28/90)
RS/6000 virtual addressing (0 replies, 02/28/90)
RISC basic material (0 replies, 02/28/90)
68040 two-way pipeline (0 replies, 02/28/90)
Portability (0 replies, 03/01/90)
benchmarking (35 replies, 03/01/90)
Segments (1 reply, 03/01/90)
i860 double multiply (0 replies, 03/01/90)
Semaphores without Test&Set instruction (1 reply, 03/01/90)
Inverted Page Tables and Object Oriented Systems (0 replies, 03/01/90)
DataBase Machines (3 replies, 03/01/90)
Official comments on recent ARM postings (5 replies, 03/01/90)
Lisa Clock Rate (0 replies, 03/01/90)
Neal Nelson Benchmarks (9 replies, 03/01/90)
Query: memory architecture for high-speed random access (0 replies, 03/01/90)
Cache Size (8 replies, 03/02/90)
New instructions for RISCs (14 replies, 03/02/90)
68040 overview? (2 replies, 03/02/90)
byte rate measurement semantics: MB/s vs. B/uS (0 replies, 03/02/90)
Where are all the ARM postings? (0 replies, 03/02/90)
Prefetch instruction (2 replies, 03/02/90)
Who are you calling English? (0 replies, 03/02/90)
Networking and Re: Yet Another Killer Micro? (0 replies, 03/02/90)
Inverted Page Tables (8 replies, 03/03/90)
References for "atypical" compilers. (2 replies, 03/03/90)
more on i860 mulitply (0 replies, 03/04/90)
hmmm, BitBlt, One-cycle bitblt by Chor et al. (1 reply, 03/04/90)
Diagrams/detail describtion on parallel arch (0 replies, 03/04/90)
IBM RISC (27 replies, 03/04/90)
Floating Point Multipliers (1 reply, 03/05/90)
BitBlt, new instructions for RISC. (5 replies, 03/05/90)
Recent Posting on Fork (0 replies, 03/05/90)
Yet Another Killer Micro? (7 replies, 03/06/90)
What's a personal computer (2 replies, 03/06/90)
Info on Barrel Processors wanted (4 replies, 03/06/90)
Databases and comp.arch (0 replies, 03/06/90)
Standard Terminology? (0 replies, 03/06/90)
What does VLIW stand for? (8 replies, 03/06/90)
heaps of numbers (2 replies, 03/06/90)
Looking for SPECmark data with system configurations (0 replies, 03/06/90)
64-bit addresses (84 replies, 03/06/90)
IBM RISC System/6000 AS/400 (17 replies, 03/07/90)
Signetics VLIW (1 reply, 03/07/90)
Copy-On-Write (0 replies, 03/07/90)
John Mashey (3 replies, 03/07/90)
floating point formats -- usage of small floats (5 replies, 03/07/90)
HOT CHIPS 2 (0 replies, 03/07/90)
CORRECTION to: heaps of numbers (3 replies, 03/08/90)
Modulus (8 replies, 03/10/90)
Call for discussion: comp.sys.ibm.rs6000 (0 replies, 03/11/90)
Byte Unix Benchmarks was <Re: RISC/6000 benchmark results> (0 replies, 03/15/90)
CDC Scoreboard reference (1 reply, 03/15/90)
Byte UNIX Benchmarks (4 replies, 03/15/90)
Archiving Comp.Arch out there on the Internet? (0 replies, 03/15/90)
Address to come from's home a time's (0 replies, 03/16/90)
Floating point register renaming (3 replies, 03/16/90)
SPECs and DBMS (3 replies, 03/17/90)
Indirect addressing on SIMD architectures (2 replies, 03/17/90)
Register Window Benchmarks (0 replies, 03/17/90)
Loose vs Tight coupling for OLTP (0 replies, 03/17/90)
Portable Unix boxes was "Killer Micros" (4 replies, 03/17/90)
RISC SYSTEM/6000 BENCHMARK (0 replies, 03/18/90)
The ENIAC & Decimal Arithmetic (0 replies, 03/18/90)
yet-another-benchmark (10 replies, 03/18/90)
Acorn's RISC family (0 replies, 03/19/90)
New Release of AE Program Profiling System (0 replies, 03/19/90)
why tagged immediate floats are good (4 replies, 03/19/90)
Polymorphism (0 replies, 03/19/90)
Portable Unix boxes (1 reply, 03/20/90)
Dual FPUs? (4 replies, 03/20/90)
SIMULATORS FOR COMPUTER ARCHITECTURES (0 replies, 03/20/90)
Benchmarks for Register Windows Study (2 replies, 03/20/90)
To desktop or not to desktop? (0 replies, 03/20/90)
Info on new IBM RISC (0 replies, 03/21/90)
Decimal Arithmetic and number of bits-per-character. (0 replies, 03/21/90)
Decimal Arithmetic (5 replies, 03/21/90)
Dynamic internal state (7 replies, 03/21/90)
Latest SPECmarks? (0 replies, 03/21/90)
On-chip caches using DRAM cells (0 replies, 03/21/90)
load instruction on MIPS R2000 and R3000 (3 replies, 03/21/90)
Wanted - System Characterization Benchmarks (0 replies, 03/21/90)
Killer Micros and vectorized code (19 replies, 03/21/90)
Cyber 992 (0 replies, 03/21/90)
Killer micros clarification (1 reply, 03/21/90)
IBM S/360 FP (2 replies, 03/22/90)
Fair-share scheduler (0 replies, 03/22/90)
Shock! RISC graphics cards for Macs before AMD! (0 replies, 03/22/90)
*MY* machine (0 replies, 03/23/90)
New RISC Graphics for Macs (8 replies, 03/23/90)
Killer Micros and the TC2000 (4 replies, 03/23/90)
RS6000 Multiply/Accumulate instruction (4 replies, 03/23/90)
Motorola Delta mips-ratings versus new MPC mips-ratings (3 replies, 03/23/90)
Centralized vs distributed computing (5 replies, 03/23/90)
Why The Move To RISC Architectures? (14 replies, 03/23/90)
function calls (1 reply, 03/23/90)
68040 Transparent Translation problem (0 replies, 03/26/90)
Polymorphic type checking (0 replies, 03/29/90)
Sure, with a CM (0 replies, 03/29/90)
CDC nostalgia (0 replies, 03/30/90)
net gaff (0 replies, 04/01/90)
ROM-based compression algorithm (0 replies, 04/05/90)
380,000 MegaByte Drive (0 replies, 04/06/90)
Skunk works (0 replies, 04/07/90)
ftp SPEC numbers (0 replies, 04/08/90)
Benchmark info for the new DECstation 5000 (2 replies, 04/09/90)
Dram Capacitance (1 reply, 04/09/90)
16M DRAM (3 replies, 04/09/90)
dataflow researchers e-mail address (0 replies, 04/10/90)
RISCy question (0 replies, 04/10/90)
Questions about DRAM's (2 replies, 04/10/90)
Capabilities and Object Oriented Programming (5 replies, 04/10/90)
Looking for research being done in parallel processing (0 replies, 04/11/90)
$5000 workstation (0 replies, 04/11/90)
RISC and Video "Where" Question (0 replies, 04/11/90)
IBM RS6000 POWER Information (1 reply, 04/11/90)
what's the difference between a PC and a workstation? (0 replies, 04/11/90)
"zero wait states" (2 replies, 04/11/90)
$5000 workstations (4 replies, 04/11/90)
Parallel cache and TLB lookup (1 reply, 04/11/90)
subscription trouble (0 replies, 04/11/90)
OS/2, PC's, etc... (1 reply, 04/11/90)
In Search of Hardware Description Programs (0 replies, 04/11/90)
Capabilities and Object Oriente (0 replies, 04/11/90)
Acorn Archimedes (1 reply, 04/12/90)
Evolution of X terminals (0 replies, 04/12/90)
Single user vs. shared (50 replies, 04/12/90)
foolish Japan bashing (0 replies, 04/12/90)
Connection Machines -- worthwhile or what? (0 replies, 04/12/90)
The infamous JARGON FILE is being revised -- send us your slang (0 replies, 04/13/90)
Ethernet Factoid (6 replies, 04/13/90)
publisher anyone? (1 reply, 04/13/90)
Hennessy & Patterson Computer Architecture book: book-signing (0 replies, 04/13/90)
Block-mode Linear Algebra (0 replies, 04/13/90)
Cost per Pixel (1 reply, 04/14/90)
CDC/Cray Museum (2 replies, 04/14/90)
GUI Benchmark (1 reply, 04/14/90)
Future of binary compatibility for unix? (1 reply, 04/14/90)
Get a Job in Canada?! (1 reply, 04/14/90)
Black magic, IBM RIOS. (9 replies, 04/14/90)
now 15.8 is almost 27.5??? (1 reply, 04/15/90)
riscy CISC (1 reply, 04/15/90)
CDC 6600 and its compilers (1 reply, 04/15/90)
Multi-Ported Register File (3 replies, 04/15/90)
ACM ICS'90-LAST CALL FOR REGISTR. (0 replies, 05/02/90)
What they tried to do to the ETA 10 (0 replies, 05/02/90)
Scalability? (1 reply, 05/02/90)
LAST call for papers, TAI90 (0 replies, 05/02/90)
Upgrades via zero-ohm resistor changes (1 reply, 05/03/90)
further super adventures (0 replies, 05/03/90)
Multiuser Performance of DECstation 5000 (0 replies, 05/03/90)
Specmarks wanted (0 replies, 05/03/90)
Decoded I-Cache (0 replies, 05/04/90)
WANTED: Research papers on memory/DRAM access tweaks (1 reply, 05/04/90)
Price/Performance of DECsystems (3 replies, 05/04/90)
29000 traps (0 replies, 05/04/90)
Multiprocessing in your own PC lab (6 replies, 05/04/90)
Back to Basics, Which Flip Flop Do you use ? (1 reply, 05/04/90)
RISC definition (6 replies, 05/04/90)
The Nth Generation (0 replies, 05/04/90)
What they did to the 370 (2 replies, 05/05/90)
benchmark source (0 replies, 05/05/90)
68040 LINPACK numbers from Microprocessor Forum (1 reply, 05/06/90)
Seeking advice on Transputer config. for signal proc. (0 replies, 05/07/90)
Any SPEC marks for Intel 80x86 Processors? (1 reply, 05/07/90)
i860 benchmarks? (4 replies, 05/08/90)
partial writes (0 replies, 05/08/90)
Decoding in I-cache (1 reply, 05/08/90)
VHDL descriptions of existing IC's ? (0 replies, 05/08/90)
Performance (4 replies, 05/08/90)
Info. on DEC's Mass Storage Protocol (3 replies, 05/08/90)
SPEC, SPECthruput (1 reply, 05/09/90)
Compiler Optimizations (0 replies, 05/09/90)
QUEUEING NETWORK THEORY (0 replies, 05/09/90)
Compile Times on BIG Basic Blocks (3 replies, 05/10/90)
Yet another upgrade story-- in software (3 replies, 05/10/90)
Non-Discoid Very Large Mass Storage Systems (1 reply, 05/10/90)
The Sixth Generation (12 replies, 05/10/90)
Request for protocol overhead references (0 replies, 05/23/90)
Nexgen (0 replies, 05/24/90)
S-100 and PC DOS (0 replies, 05/25/90)
S100 boxes (0 replies, 05/25/90)
Xenix address space (0 replies, 05/25/90)
TLB freezeup? (0 replies, 05/26/90)
Yet Another Upgrade Anecdote (27 replies, 05/26/90)
680x0 upwards compatability (1 reply, 05/26/90)
6th Generation, Newspaper Article (1 reply, 05/28/90)
Why IBM went for the 8088 -- The Untold Story (10 replies, 05/29/90)
Paper in Euromicro 90 (0 replies, 05/29/90)
32016 PC-relative (1 reply, 05/29/90)
Winter Usenix '91: CALL FOR PAPERS (0 replies, 05/30/90)
dynamic linking, was 32016 PC-relative (0 replies, 05/30/90)
Old (1 reply, 05/30/90)
PDP-11s (1 reply, 05/30/90)
National 32000 UNIX history (0 replies, 05/30/90)
RS/6000 Instruction Set Reference (1 reply, 05/30/90)
disk allocation strategy (2 replies, 05/30/90)
386 and ugliness (1 reply, 05/30/90)
Adam Smith's Hand (3 replies, 05/30/90)
Miscellaneous 8086 History (1 reply, 05/30/90)
Publish date of Lampson-Sproull paper (0 replies, 05/31/90)
Unexpected CPU behavior and the CLR instruction (1 reply, 05/31/90)
MP Locking Fine Grain or Course -> Coarse (1 reply, 05/31/90)
SPEC (0 replies, 05/31/90)
thinking small about X... (2 replies, 05/31/90)
80386 questions (0 replies, 05/31/90)
The curious floating-point arithmetic on the IBM RS6000 (0 replies, 05/31/90)
Microprocessors and market forces (3 replies, 05/31/90)
Definition of "OS"? (0 replies, 05/31/90)
New workstations and SCSI peripherals (1 reply, 06/01/90)
New Intel CPU's First Appearance (1 reply, 06/01/90)
Info on hardware for real-time database applications (0 replies, 06/01/90)
HOT CHIPS SYMPOSIUM --- HOT CHIPS II (0 replies, 06/01/90)
The invisible hand of Adam Smith (0 replies, 06/01/90)
Status of VMEbus mailing list? (0 replies, 06/01/90)
RISC/CISC Philosophies (0 replies, 06/02/90)
IBM 4381/P22 vs. /P23 (0 replies, 06/02/90)
MIPS 64x32 Divide? (2 replies, 06/02/90)
Device Driver Needed: SCO V/386 - Exabyte 8200S Tape Drive (0 replies, 06/02/90)
Benchmarks wanted (3 replies, 06/02/90)
Orphaned Response (4 replies, 06/02/90)
CMs, CAMs, etc (0 replies, 06/02/90)
Series 32000; alive and well (2 replies, 06/02/90)
Does anyone know anything about the N-Cubed Hypercube? (2 replies, 06/02/90)
Cache structure on SPARC machines (0 replies, 06/02/90)
comments to benchmark and results (0 replies, 06/02/90)
Personal OS (13 replies, 06/03/90)
The invisible hand of Adam Smit (6 replies, 06/04/90)
64 by 32 divide needs 64 bit datapath? (0 replies, 06/04/90)
Re^2: Superlinear Speedup (3 replies, 06/04/90)
Direct Mapped Caches (0 replies, 06/04/90)
Superlinear Speedup (3 replies, 06/05/90)
Re^4: Superlinear Speedup (0 replies, 06/05/90)
Alliant FX/8 Cache Info Needed (1 reply, 06/05/90)
Follow comments to remarks by Dave Patterson at ISCA in Seattle (0 replies, 06/05/90)
Can anyone offer help/info on Weitek XL8032 chip? (0 replies, 06/05/90)
Books... (0 replies, 06/05/90)
Question on division methods (2 replies, 06/06/90)
Trivia Question; what's inside a Sun 3/75? (0 replies, 06/06/90)
Exceptions in IEEE 754 Arithmetic (0 replies, 06/06/90)
Interesting Memory Devices (0 replies, 06/06/90)
Standard DMA architectures (0 replies, 06/06/90)
Course Announcement (0 replies, 06/07/90)
The invisible nose of Adam Smith (0 replies, 06/07/90)
Speed costs (26 replies, 06/07/90)
Large executables: Where's the space going? (4 replies, 06/07/90)
Write-Back, Write-Allocate Policies (1 reply, 06/07/90)
Transformation Systems? (0 replies, 06/07/90)
Wanted: 68000 assembler (0 replies, 06/08/90)
unexpected CPU behavior was 486 bugs -- it's in there! (17 replies, 06/08/90)
300K for a clock. (0 replies, 06/08/90)
A short note on posting (5 replies, 06/08/90)
GNUemacs , SysV, and paging (0 replies, 06/08/90)
Randomised Instruction Set Computer (8 replies, 06/09/90)
unexpected CPU behavior (0 replies, 06/09/90)
ATTENTION all digital CHIP DESIGNERS : Help Requested (1 reply, 06/09/90)
Benchmark figures of MIPS6000/6010? (1 reply, 06/09/90)
Me too. (0 replies, 06/09/90)
300K for a clock actually, PLEASE GET comp.arch BACK TO NORMAL! (0 replies, 06/10/90)
Benchmarking minisupers... (1 reply, 06/10/90)
I/O subsystems (0 replies, 06/10/90)
Real disk FASTER than Ram disk (12 replies, 06/10/90)
Smart Linking (3 replies, 06/11/90)
Request for help/info on Weitek XL8032 RISC chip (0 replies, 06/11/90)
RISC vs CISC simple load benchmark; amazing ! (0 replies, 06/11/90)
Timers on Suns/Sparcs (1 reply, 06/12/90)
Hennessey (5 replies, 06/12/90)
Architectural Requirements for Unix (10 replies, 06/12/90)
Parallaxis - new version (0 replies, 06/12/90)
Arrgghhh! (0 replies, 06/12/90)
notes on 64Mbit DRAM paper from Hitachi (0 replies, 06/13/90)
i860 registers/chip in general (5 replies, 06/13/90)
Fast Data transfer between ATs (2 replies, 06/13/90)
A draft of the revised JARGON FILE has been posted. (0 replies, 06/13/90)
Intel-Touchstone (0 replies, 06/13/90)
On Chip Emulator (3 replies, 06/14/90)
Synchronization primitives and cache coherence (3 replies, 06/14/90)
Why RAMs are 1 bit wide (0 replies, 06/14/90)
AT&T's 1-4 Processor StarServer (0 replies, 06/14/90)
88k vs. i860 for a shared memory parallel processor running (0 replies, 06/14/90)
QCDPAX (0 replies, 06/14/90)
Re^2: Macintosh OS (7 replies, 06/15/90)
88k vs. i860 for a shared memory parallel processor running MACH (3 replies, 06/15/90)
88100 exception processing (0 replies, 06/15/90)
Program to discern machine architecture information (2 replies, 06/15/90)
lets start another processor war - i860 vs RIOS (1 reply, 06/16/90)
i860 registers, follow up (1 reply, 06/16/90)
Superscaler info needed (0 replies, 06/16/90)
ECC (3 replies, 06/16/90)
Superlinear speed-up (0 replies, 06/16/90)
Processor architecture to support functional languages (4 replies, 06/16/90)
Macintosh OS (63 replies, 06/17/90)
2 bit DRAM (0 replies, 06/17/90)
1st 64 Megabit DRAM (14 replies, 06/17/90)
Multi-tasking, and immunology (3 replies, 06/18/90)
RISC vs CISC simple load benchmark; amazing ! Not really (6 replies, 06/18/90)
Hardware mice pointers (10 replies, 06/21/90)
88k Hypermodule? (0 replies, 06/25/90)
Wide DRAMs (0 replies, 06/26/90)
Splitting comp.arch into sub groups (0 replies, 06/27/90)
Putting libc.a into a segment (3 replies, 06/27/90)
XOR cursors (4 replies, 06/28/90)
reference needed: Attack of the Killer Micros (0 replies, 06/28/90)
ATTENTION all digital CHIP DESIGNERS - a summary (0 replies, 06/28/90)
SPARC multiply-step instruction (1 reply, 06/28/90)
Patents, bogus lawsuits, & etc. (0 replies, 06/28/90)
486 bugs -- it's in there! (3 replies, 06/28/90)
Inherent imprecision of floating point variablesREAD/NEW (1 reply, 06/28/90)
Tradeoffs (16 replies, 06/28/90)
MIPS second-sourcing (0 replies, 06/29/90)
Arithmetic Instructions (0 replies, 06/29/90)
New SPARC instructions (0 replies, 06/29/90)
TLB problem (0 replies, 06/30/90)
"Attack of the Killer Micros" on TV (0 replies, 07/01/90)
compiling bitblt and instruction cache (1 reply, 07/02/90)
Parallel CRC Implementation (1 reply, 07/03/90)
need of cache and virtual memory simulator (0 replies, 07/03/90)
ISCA'90 (0 replies, 07/03/90)
Instruction caches and closures - why two caches??? (0 replies, 07/03/90)
Bloat costs (32 replies, 07/03/90)
Computer Patents (1 reply, 07/03/90)
Patents and Misinformation (5 replies, 07/03/90)
Patents and MisinformationSKIP (0 replies, 07/04/90)
Using a Sparc for Embedded Control (0 replies, 07/04/90)
Fortran (0 replies, 07/04/90)
Computers and brainpower (0 replies, 07/04/90)
SUMMARY: Arch. Support for OOL's (0 replies, 07/04/90)
Patents and Architecture: can't patent use of transistors... (0 replies, 07/05/90)
Request for information (0 replies, 07/05/90)
Mixing paging and IO is inefficient (7 replies, 07/05/90)
Question on Gfx processors (0 replies, 07/06/90)
Paging page tables & SUN4s (3 replies, 07/07/90)
Fork and exec, was Paging page tables & SUN4s (0 replies, 07/07/90)
Speed Kills (13 replies, 07/09/90)
Instruction caches and closures (9 replies, 07/09/90)
Did you attend the panel sessions of ISCA'90? (0 replies, 07/09/90)
i860 cc/The Portland Group (0 replies, 07/10/90)
Spinlock for MIPS R3000 (0 replies, 07/10/90)
Thanks.. (0 replies, 07/11/90)
Article from Acorn (0 replies, 07/11/90)
Technology Transfer Mailing List (0 replies, 07/12/90)
i860 compilers summary (0 replies, 07/12/90)
Paging page tables (30 replies, 07/12/90)
global optimization (2 replies, 07/12/90)
AMD29000 and IBM RIOS and ROMP chip description paper wanted (0 replies, 07/13/90)
fork and preallocation -- paging anywhere handy (0 replies, 07/13/90)
VLSI for AI and Neural Nets Workshop. Oxford, England Sept.'90 (0 replies, 07/14/90)
``Strange instructions'' (1 reply, 07/14/90)
Chess Machines (0 replies, 07/14/90)
Micrprocessor Forum Advance Program (1 reply, 07/14/90)
Fast Re-booting (0 replies, 07/14/90)
The CS "religion" (0 replies, 07/14/90)
Compiler Costs -- profiling (0 replies, 07/15/90)
386 machines are workstations? (22 replies, 07/16/90)
Hot Spots (1 reply, 07/16/90)
An example of a program (1 reply, 07/16/90)
New language for Parallel Processing - SEZ.YALE. (0 replies, 07/16/90)
Vector_Assembly (1 reply, 07/16/90)
Overwhelming demand for Ease Report - SEZ.YALE. (0 replies, 07/17/90)
Mercury delay lines (28 replies, 07/17/90)
Inlining subroutines at link time (15 replies, 07/18/90)
68040 alive? was: Re: Moto's data predicts 68040 . . .) (0 replies, 07/18/90)
Computer Architecture methodology (9 replies, 07/18/90)
i860 flush instruction obscurities - HELP! (3 replies, 07/18/90)
Threaded "interpreters" (0 replies, 07/19/90)
Register Allocation and Aliasing (12 replies, 07/20/90)
World's Cheapest Unix Engine (8 replies, 07/20/90)
MMU detection of stack/heap overflow: summary of responses (0 replies, 07/20/90)
Motorola 68040 (2 replies, 07/21/90)
Beating pinout by voltage domain multiplexing (6 replies, 07/22/90)
vfork (32 replies, 07/23/90)
Unstructured Programming (0 replies, 07/23/90)
68K stack puke (0 replies, 07/24/90)
Is CS a misnomer? (0 replies, 07/24/90)
Moto's data predicts 68040 performance well below 20 MIPS (15 replies, 07/24/90)
fork (12 replies, 07/24/90)
religion and computer science (5 replies, 07/24/90)
The Bus Abandonment Lock (0 replies, 07/24/90)
Fast /tmp (8 replies, 07/24/90)
Understanding computers and programming (0 replies, 07/24/90)
Teaching Programming (0 replies, 07/24/90)
fork and preallocation (11 replies, 07/25/90)
Once more into the niche! (2 replies, 07/25/90)
Patents and Architecture (40 replies, 07/25/90)
GC triggering and stack limit checking by MMU hardware (15 replies, 07/25/90)
RISC hard to program? (24 replies, 07/25/90)
LINPACK 1000x1000 MFLOPS per $$$ (12 replies, 07/26/90)
Misaligned accesses (0 replies, 07/26/90)
taxonomy for superscalars/etc (5 replies, 07/26/90)
Compress, LZW and LZ... (0 replies, 07/26/90)
SPECmark for Sun SPARCstation SLC wanted (1 reply, 07/26/90)
It looks like he's at it again! (45 replies, 07/26/90)
File system consistency. (0 replies, 07/26/90)
Looking for good book to learn/teach 80386 assembler on AT&T6386 (0 replies, 07/26/90)
Compiler Costs (53 replies, 07/27/90)
Closing keywords (0 replies, 07/27/90)
RS/6000 renaming (5 replies, 07/27/90)
i860 compiler info. needed (0 replies, 07/28/90)
Peltier cooler (5 replies, 07/28/90)
RS/6000 XL compilers (0 replies, 07/28/90)
Introducing Bonnie - Unix filesystem bottleneck finder (0 replies, 07/30/90)
Moto's data predicts 68040 performa (1 reply, 07/30/90)
Voltage multiplexing (0 replies, 07/30/90)
He's not the only one at it again! (13 replies, 07/31/90)
High-Priority Instructions (7 replies, 07/31/90)
Government Sponsored Technology Development Grants (0 replies, 07/31/90)
Seeking Parallel Programs (0 replies, 08/01/90)
pointer to LZW compression patent discussion (0 replies, 08/01/90)
TI 99/4 speed (5 replies, 08/01/90)
Benchmarking interactive software (2 replies, 08/01/90)
Text book suggestions... (0 replies, 08/02/90)
Disk drives. (2 replies, 08/02/90)
Algol was an advance, was He's not the only one at it again! (4 replies, 08/02/90)
Info needed about i860 compilers (0 replies, 08/02/90)
Looking for literature on 64-bit paging schemes (0 replies, 08/02/90)
Electro-optic bus (22 replies, 08/03/90)
Why not evacuate Disk drives. (6 replies, 08/03/90)
Request for disk access traces (0 replies, 08/03/90)
moving laser beams, not media (1 reply, 08/03/90)
Book on Verilog HDL (1 reply, 08/03/90)
Comparison operators (5 replies, 08/03/90)
Sir Clive Sinclair's 200 MIP computer (1 reply, 08/03/90)
stigma of Parallel Programs (1 reply, 08/03/90)
Re Re: Looking for literature on 64-bit paging schemes (0 replies, 08/04/90)
disk rotation speed (6 replies, 08/04/90)
Tiny paper tapes (0 replies, 08/04/90)
Disk with 2 HDA (1 reply, 08/04/90)
Mario Bothers (11 replies, 08/05/90)
What's wrong with CRT storage? (3 replies, 08/05/90)
drive rpm (0 replies, 08/06/90)
I'm back.... (0 replies, 08/06/90)
Threaded interpretive languages and other such ilk (0 replies, 08/06/90)
Fish Stew (2 replies, 08/06/90)
Mips at 150 mips ??? (1 reply, 08/06/90)
CFP Winter Usenix 2nd Call (0 replies, 08/06/90)
Call for Discussion: comp.benchmarks (0 replies, 08/06/90)
Really Modular Software (0 replies, 08/06/90)
fork, spawn, vfork: an overview -- is this confused?? (0 replies, 08/07/90)
seeking general purpose workstation w/large memory (2 replies, 08/07/90)
Spawn is impossible to define (15 replies, 08/07/90)
Algol, and language design (3 replies, 08/07/90)
CFP - Int'l Symp. on Computer Architecture (0 replies, 08/08/90)
PLEDGE FOR SCIENCE IN ARGENTINA (0 replies, 08/08/90)
resuming after fault (1 reply, 08/08/90)
fork, spawn, vfork: an overview (10 replies, 08/09/90)
Extremely Large Files (0 replies, 08/09/90)
New newsgroup (1 reply, 08/10/90)
Big files, and lots of 'em: 32 bits is not enough (3 replies, 08/10/90)
Data Storage density questions (28 replies, 08/11/90)
do chip timing specs mean anything (1 reply, 08/11/90)
Electro-Optic Busses (0 replies, 08/11/90)
Missing .Signature (0 replies, 08/11/90)
Drives in IBM RS/6000. (0 replies, 08/11/90)
i860 instruction cache (0 replies, 08/12/90)
All those bits (1 reply, 08/12/90)
Extremely Fast Filesystems (40 replies, 08/13/90)
Crash a RISC machine.... (0 replies, 08/13/90)
64-bit microprocessors (0 replies, 08/13/90)
Ease Status Update (0 replies, 08/14/90)
Unaligned Data Trapping -- Highly Useful for Lisp (0 replies, 08/14/90)
HyperStone info desired (0 replies, 08/14/90)
386 chip "hangs" when in protected mode and 387 in place SCO Xenix (3 replies, 08/14/90)
Looking for Remote Terminal Emulation Benchmarks (0 replies, 08/14/90)
Needed - VME Bus & Tag Printer Interface (0 replies, 08/15/90)
64 bits, but for what? (3 replies, 08/15/90)
"Wedging RISC machines" was (0 replies, 08/16/90)
i860 Compilers -- Summary (0 replies, 08/16/90)
MUSBUS benchmark program (0 replies, 08/16/90)
Comp.arch Archives ???? (0 replies, 08/16/90)
Crash a RISC machine from user-mode code: (0 replies, 08/17/90)
I crashed our MIPS machine today (3 replies, 08/17/90)
comp.benchmarks (0 replies, 08/17/90)
64 bits - LOTS of memory ain't necessary wonderful (1 reply, 08/17/90)
[comp.arch...] SCSI (0 replies, 08/17/90)
386 chip "hangs" when in protected mode and 387 in place SC (4 replies, 08/18/90)
why SCSI is good (0 replies, 08/18/90)
comp.benchmark (3 replies, 08/19/90)
Request for info.comp.arch (0 replies, 08/20/90)
Any MAGIC wizards out there ? (0 replies, 08/20/90)
"Smart" cache re-loading (0 replies, 08/21/90)
SCSI (3 replies, 08/21/90)
"Hot patching" - who does it? (0 replies, 08/21/90)
VME cards / drivers (0 replies, 08/21/90)
Home grown RISC, market survey (1 reply, 08/22/90)
Instruction Set Level Simulator (0 replies, 08/22/90)
Is handling off-alignment impor (9 replies, 08/22/90)
COFF and >32-bit addressses? (0 replies, 08/22/90)
Current Microprocessors (3 replies, 08/22/90)
VLSI for AI and Neural Nets Workshop. Oxford, Sept. 5-7 (0 replies, 08/22/90)
Cooled Processors (0 replies, 08/22/90)
Performance evaluation mailing list (1 reply, 08/23/90)
64-bits (4 replies, 08/23/90)
Info. on MOSIS (0 replies, 08/23/90)
Architectural quirks (4 replies, 08/23/90)
64 bit clocks (1 reply, 08/24/90)
Do chip timing specs mean anything? (19 replies, 08/24/90)
Fabbing Chips (0 replies, 08/24/90)
Request to Caltech Students/Staff/C.R.Lang Jr. (0 replies, 08/24/90)
VLSI (0 replies, 08/25/90)
NACLP Workshop on Prolog Architectures & Compilers (0 replies, 08/25/90)
NMI bug (0 replies, 08/25/90)
Computer time measurements (8 replies, 08/27/90)
RAM controller for 68k? (3 replies, 08/27/90)
Has the Mip R4000 been announced yet? (1 reply, 08/27/90)
AS/400, single level store, 64 bits (0 replies, 08/27/90)
Recent benchmarks on Intel i860? (0 replies, 08/27/90)
time of year clocks (2 replies, 08/28/90)
was MIPS R[236]000 interrupts (1 reply, 08/28/90)
Accurate computations (0 replies, 08/28/90)
Why not 48-bit processors? (1 reply, 08/29/90)
CFP: 1991 International Conference on Supercomputing (0 replies, 08/29/90)
Call for discussion: COMP.SYS.IBM.RISC6000 (0 replies, 08/29/90)
Synchronising Clocks. (2 replies, 08/30/90)
Cyber 205 arithmetic (0 replies, 08/31/90)
64 bits for times.... (29 replies, 08/31/90)
How fast is fast? (1 reply, 08/31/90)
Benchmarks from Hell (3 replies, 08/31/90)
Disk Mirroring (0 replies, 08/31/90)
VM traces (0 replies, 08/31/90)
DEC printer info needed (0 replies, 09/01/90)
Scalable Coherent Interface Protocol (0 replies, 09/01/90)
modulo/remainder: it's all division (0 replies, 09/02/90)
Fuzzy Processors (5 replies, 09/02/90)
i860 performance figures -- finally (0 replies, 09/03/90)
Object atomicity for multiprocessor hardware (0 replies, 09/04/90)
Hardware Magazines (3 replies, 09/04/90)
CLIPPER bit test (1 reply, 09/05/90)
New release of SPIM (0 replies, 09/05/90)
bit addressing (0 replies, 09/05/90)
64 bits (38 replies, 09/06/90)
AMD 29000 (3 replies, 09/07/90)
Intel and end-users. (0 replies, 09/07/90)
Further i860 benchmarks: NAS Kernels (0 replies, 09/07/90)
Timers (3 replies, 09/07/90)
What *should* architectural pointers point at? (22 replies, 09/10/90)
Floating Point is Here to Stay (0 replies, 09/10/90)
hardware multiply/divide (0 replies, 09/10/90)
Integer multiply in address arithmetic (0 replies, 09/11/90)
68040 vs 68882 on transcendentals (0 replies, 09/11/90)
residue arithmetic (0 replies, 09/12/90)
RISCy designs (0 replies, 09/12/90)
Why FP at all? (14 replies, 09/12/90)
Killer Micro II (39 replies, 09/12/90)
Is handling off-alignment important? (43 replies, 09/12/90)
Add with carry (0 replies, 09/13/90)
Throwaway: Speedup address formation for cache lookup (2 replies, 09/14/90)
Architecture questions (13 replies, 09/14/90)
What about hardware implementations of optimized algorithms? (5 replies, 09/14/90)
68040 where is it? (12 replies, 09/14/90)
FFT break-even point (0 replies, 09/15/90)
special instructions for checksums (0 replies, 09/15/90)
RISC pipelines (1 reply, 09/17/90)
seeking for a 8049 cross-assembler (0 replies, 09/17/90)
Full-Custom VLSI Design -- Employment Wanted. (0 replies, 09/17/90)
int x int -> long for * (18 replies, 09/17/90)
Why floating point hardware: micro-parallelism, micro-cycles (7 replies, 09/18/90)
importance of carry logic (1 reply, 09/18/90)
Interrupts in user space and precise traps (0 replies, 09/18/90)
Architecture specific OS features (0 replies, 09/19/90)
Partitioning and Scheduling for Heterogeneous Systems (0 replies, 09/19/90)
Seeking Soviet Readership (2 replies, 09/19/90)
RISC vs. CISC? No, OS bug executing data... (7 replies, 09/19/90)
MISC (6 replies, 09/19/90)
hardware vs software upgrades (0 replies, 09/19/90)
single register window sparc (1 reply, 09/20/90)
End-of-buffer interrupt instruction (8 replies, 09/20/90)
64 bits--why stop there? (62 replies, 09/20/90)
Request for info: Retargetable Optimizing Assemblers (0 replies, 09/20/90)
MIPS R[236]000 interrupts (5 replies, 09/20/90)
How cheap can prototype chips be built for? (1 reply, 09/20/90)
Latest PSEC numbers? (0 replies, 09/20/90)
benchmark for evaluating extended precision (17 replies, 09/20/90)
Interrupts in user space (9 replies, 09/20/90)
Lectureship in Computer Engineering @ Manchester University UK (0 replies, 09/20/90)
memory accesses, parity, etc. (0 replies, 09/21/90)
Recent discussion on timer/timing facilities (0 replies, 09/21/90)
Wanted: Symbolic Debugger for IBM System 370 Machine (1 reply, 09/22/90)
Seeking Industrial Support for Research on "Intelligent Memory" (0 replies, 09/22/90)
Kahaner Report: Optical computing in Japan (1 reply, 09/22/90)
Workstation Data Integrity (74 replies, 09/25/90)
New ARM machines (0 replies, 09/25/90)
64-bit EDC (0 replies, 09/25/90)
Alignment IS important (1 reply, 09/26/90)
Discontinuity (1 reply, 09/26/90)
Parallel Tracefile Standards? (0 replies, 09/26/90)
Acorn Archimedes FTP sites (0 replies, 09/26/90)
Cache On Chip (0 replies, 09/26/90)
F.P. vs. arbitrary-precision (29 replies, 09/26/90)
Acorn RISC Machine memory management (6 replies, 09/26/90)
Sparc strangeness (0 replies, 09/26/90)
Discontintuiy (3 replies, 09/27/90)
Looking for Virtual Machine Bibliogaphy (0 replies, 09/27/90)
Microprocessor Forum Final Program (1 reply, 09/27/90)
benchmarks for Multy cpu wanted. (1 reply, 09/28/90)
Literature on Inverted Page Tables (0 replies, 09/28/90)
Summary of References on Partitioning and Scheduling w/ Heterogeneity (0 replies, 09/28/90)
DEC Workstations (2 replies, 09/29/90)
Commercial Benchmark Suites (0 replies, 09/29/90)
cas for VAX (0 replies, 09/29/90)
Historical architectural advances??? (3 replies, 09/29/90)
Parallel hardware for undergraduate instruction (3 replies, 09/30/90)
Call for Votes: comp.benchmarks (2 replies, 10/01/90)
GE Instruction Set (2 replies, 10/01/90)
cost effectiveness of shared memory (0 replies, 10/02/90)
Interrupts in user space; Lightweight Traps (4 replies, 10/02/90)
DLX Simulator Users (0 replies, 10/03/90)
Need definition for "sentry file" (0 replies, 10/03/90)
Cache Line Fills -- Critical Word First (10 replies, 10/04/90)
the new NeXT machine (4 replies, 10/04/90)
inequality vs. less-than (2 replies, 10/04/90)
Bendix G15 (0 replies, 10/05/90)
Novice question (0 replies, 10/05/90)
numeric comparison (1 reply, 10/05/90)
Cypress CY7C605 MP CMMU - is it out yet (1 reply, 10/05/90)
Vax benchmark references? (0 replies, 10/05/90)
Looking for a really odd vacuum cleaner (0 replies, 10/05/90)
Intel OBJ Format Documention Info Wanted (0 replies, 10/07/90)
Call for Discussion: comp.japan.research (0 replies, 10/08/90)
a style question (9 replies, 10/08/90)
intel 80960 simulation model for Mentor Graphics quicksim (0 replies, 10/08/90)
architecture independence (0 replies, 10/08/90)
Odd word size? Word size? Word? Definitely Odd. (2 replies, 10/09/90)
Nonexistent Memory (0 replies, 10/09/90)
new discussion, please! (0 replies, 10/09/90)
1620 (6 replies, 10/10/90)
Not a style question (0 replies, 10/10/90)
Book, Periodicals, and Journals on Design (0 replies, 10/10/90)
weird word lengths (4 replies, 10/10/90)
Bibliographic references to the 3M machine (0 replies, 10/11/90)
80960CA v 68040 comparative benchmark (2 replies, 10/12/90)
RAM EXPANSION (0 replies, 10/12/90)
PLEEZ somebody design something better than disk (0 replies, 10/12/90)
Looking for a really odd computer (48 replies, 10/12/90)
Looking for a PC w/ ethernet hardware built in (0 replies, 10/12/90)
IEEE Computer Special issue on Parallel Processing for Computer Vision and Image Understanding (0 replies, 10/12/90)
Shared Memory (11 replies, 10/13/90)
lisp machine arch. refs wanted (0 replies, 10/13/90)
DEC VAX striped disks (0 replies, 10/13/90)
Is 32 bits enough? (1 reply, 10/14/90)
Electrologica X8 (2 replies, 10/14/90)
Opcode assignment for RISC processors (12 replies, 10/14/90)
Workstation Disk I/O (9 replies, 10/15/90)
CALL FOR DISCUSSION: comp.sys.arm (0 replies, 10/15/90)
Model computers (0 replies, 10/15/90)
Kahaner report: Japan Info '90 (0 replies, 10/15/90)
Multiflow (3 replies, 10/16/90)
European FTP Mail Servers? (0 replies, 10/16/90)
DEC RISC Architecture? (13 replies, 10/16/90)
Info on TERA Machine Wanted (1 reply, 10/17/90)
1620 simulatore??? (2 replies, 10/17/90)
Where can I get Unix for my Archimedes? (0 replies, 10/17/90)
benchmark numbers for i860 and i960CA (0 replies, 10/18/90)
Terradata architecures (12 replies, 10/18/90)
SPECmarks for RS/6000 systems - lies??? (8 replies, 10/18/90)
pixie for SPARC? (0 replies, 10/19/90)
CALL FOR DISCUSSION: comp.lang.vhdl (0 replies, 10/19/90)
HPE Spectrum (5 replies, 10/20/90)
1620 Opcode Selection (6 replies, 10/20/90)
Data Flow Computers (3 replies, 10/21/90)
Information about new book on parallel processing and VLSI (0 replies, 10/22/90)
Standards for Multi-media (0 replies, 10/22/90)
Hardware Support for OS operations (0 replies, 10/22/90)
harvard architectures (10 replies, 10/22/90)
80486 v Sparc and other good numbers (0 replies, 10/22/90)
INFO about VAX ft 3000 (0 replies, 10/22/90)
Multiprogramming the Microcode: The B1700 (6 replies, 10/23/90)
Benchmark & Test Suites (1 reply, 10/23/90)
Has anyone heard of a system that uses Intel's 432 (0 replies, 10/23/90)
80486 v Sparc (3 replies, 10/23/90)
speculative execution (37 replies, 10/24/90)
Heterogeneous register files (0 replies, 10/24/90)
68040, 68050 (1 reply, 10/24/90)
performance and dependability measures of VAX ft 3000 (1 reply, 10/25/90)
landscape bitmapped screens (0 replies, 10/25/90)
IOStone (8 replies, 10/25/90)
Benchmark archives, was Re: IOStone (1 reply, 10/25/90)
>32 bits (2 replies, 10/25/90)
NACLP Architecture Workshop (0 replies, 10/25/90)
How about this architecture (1 reply, 10/25/90)
looking for I/O benchmark named "bonnie" (0 replies, 10/25/90)
ISP Reference? (2 replies, 10/25/90)
Perq (2 replies, 10/26/90)
64 bit sparc ship sets (7 replies, 10/26/90)
need info on Sequoia 300 (0 replies, 10/26/90)
Information sought on Intel 8089 processor : (0 replies, 10/26/90)
icache size (2 replies, 10/26/90)
Slow SPARC SLC? (1 reply, 10/27/90)
Architectural design (1 reply, 10/27/90)
m68k simulator wanted (1 reply, 10/27/90)
>32 bits: why? (2 replies, 10/28/90)
PUSH on i8088/i80x86 (15 replies, 10/28/90)
Need a special power supply. (0 replies, 10/29/90)
Looking for info on a 5-7 slot VME backplane and cage. (0 replies, 10/29/90)
Multi-precision divide with short divides? (0 replies, 10/29/90)
SUN Cache (0 replies, 10/29/90)
Status of Logic Programming and Functional Machines (0 replies, 10/29/90)
Misc. comments about MIPSCo (0 replies, 10/30/90)
Guessing Caches and Finding Their Benchmarks (0 replies, 10/30/90)
Memory mapping persistant data (1 reply, 10/30/90)
CALL FOR VOTES: comp.sys.acorn (0 replies, 10/30/90)
Call for Votes: comp.research.japan (0 replies, 10/30/90)
Associative Memories (0 replies, 10/30/90)
Need 64-bit floating point test suite (0 replies, 10/31/90)
AMD vs. Intel Arbitration (24 replies, 10/31/90)
Rumors and such in the press; believe at your peril (0 replies, 10/31/90)
CNS Program at BU Hiring 2 Assistant Professors (0 replies, 10/31/90)
Teradata (5 replies, 10/31/90)
Multi-precison divide (0 replies, 10/31/90)
Historical architectural advanc (0 replies, 10/31/90)
i860 MFLOP rate? (4 replies, 10/31/90)
AMD (0 replies, 10/31/90)
What newsgroup for the RS/6000? (1 reply, 10/31/90)
64 bit sparc chip sets (1 reply, 11/01/90)
386 Clones (9 replies, 11/01/90)
Death of SuperComputer Mfr: MYRIAS (0 replies, 11/01/90)
AMD - oops (0 replies, 11/01/90)
Numbers about workstation marketplace? (0 replies, 11/01/90)
AT-Bus workstations? (0 replies, 11/01/90)
I/O Benchmarks: Request for Information (0 replies, 11/02/90)
Loop unrolling and icache (0 replies, 11/02/90)
Fastest 88k (2 replies, 11/02/90)
intro text suggestions (4 replies, 11/02/90)
Myrias Research Placed in receivership. (1 reply, 11/02/90)
286/386 clock frequencies, highest ? + other stuff (1 reply, 11/02/90)
AT peripherals (1 reply, 11/03/90)
VAX RISC (4 replies, 11/03/90)
Un*X cost (4 replies, 11/03/90)
SPEC-benchmarks (1 reply, 11/03/90)
Is MIPS in Trouble? (9 replies, 11/03/90)
SPECthruput of SGI multiprocessors (0 replies, 11/03/90)
Is MIPS in Trouble? semi-anonymous slime attempt; good try (0 replies, 11/03/90)
FPCA '91 Call for papers (0 replies, 11/04/90)
Vittesse? (0 replies, 11/04/90)
Smart I-cache? (6 replies, 11/04/90)
Tektronix shutdown (0 replies, 11/05/90)
loadable control store, an idea whose time has gone (4 replies, 11/05/90)
SPECthruput (1 reply, 11/05/90)
Tektronix shutdown & move away from 88k's?? (26 replies, 11/05/90)
Parallel Execution of Functional Languages (0 replies, 11/06/90)
Free unix for cheap hardware (0 replies, 11/06/90)
Object Code Compression, any idea? (1 reply, 11/06/90)
Byte attempts to track down rumor sources (0 replies, 11/06/90)
IEEE floating point & various approaches; long (11 replies, 11/06/90)
Strange cache addressing algorithm (0 replies, 11/06/90)
i960CA benchmark results (0 replies, 11/06/90)
Research Leads Needed for Real-time Systems (0 replies, 11/07/90)
Anyone Archiving the comp.arch news group ????? (0 replies, 11/07/90)
PR1ME 32I mode (12 replies, 11/07/90)
Summary: pixie for SPARCs (0 replies, 11/07/90)
SUN MMU design secrets (3 replies, 11/07/90)
Registration Form and Advance Program (0 replies, 11/07/90)
Non-von Neumann machine (0 replies, 11/08/90)
processor for graphics terminal (0 replies, 11/08/90)
EFLOP architectures: when and for how much? (15 replies, 11/08/90)
Going to SuperComputing '90, but haven't registered? (0 replies, 11/08/90)
loadable control store, an idea (0 replies, 11/08/90)
RISC for Lisp (0 replies, 11/08/90)
Characters sets, screen size and resolution (0 replies, 11/09/90)
>32 bit integers (0 replies, 11/09/90)
Intel (1 reply, 11/09/90)
<None> (0 replies, 11/09/90)
Optical Computers (4 replies, 11/09/90)
The CPU from hell (0 replies, 11/09/90)
8086 compatibility (0 replies, 11/09/90)
Compilers taking advantage of architectural enhancements (25 replies, 11/09/90)
XGA (2 replies, 11/09/90)
Hennesey & Patterson Software: available via anonymous ftp (0 replies, 11/09/90)
SPEC Benchmarks (3 replies, 11/10/90)
ACM SIGSMALL Call for Papers (0 replies, 11/10/90)
compiling for multithreaded architecture (0 replies, 11/10/90)
Request for object code compression idea (0 replies, 11/10/90)
Optical link on IBM RISC 6000 (0 replies, 11/10/90)
Microprogramming Simulator wanted (0 replies, 11/10/90)
Crystal Balls (0 replies, 11/10/90)
Multiple Instruction Sets (0 replies, 11/10/90)
chip cost (6 replies, 11/10/90)
Interprocess communication (1 reply, 11/11/90)
superconcurrency and the cpu with 3 brains (2 replies, 11/11/90)
HW support for primitives (1 reply, 11/12/90)
Count Zero Interrupt + Interface (0 replies, 11/12/90)
Help needed (1 reply, 11/12/90)
PC/AT clones with RISC cpu (27 replies, 11/13/90)
automagic overlays? (4 replies, 11/13/90)
C vs. assembler was 3-headed CPUs (1 reply, 11/13/90)
The flame with 3 brains (0 replies, 11/13/90)
load delays on SPARC (1 reply, 11/13/90)
---486 compatibility with 8008 (2 replies, 11/13/90)
binary compatibility through emulation (0 replies, 11/13/90)
Research Leads Needed for Real-time (0 replies, 11/13/90)
1 double or 2 singles (7 replies, 11/14/90)
paper needed (0 replies, 11/14/90)
Historical architectural advances?? (44 replies, 11/14/90)
Faculty positions of Computer Science (0 replies, 11/15/90)
AT&T CRISP Processor (0 replies, 11/15/90)
OS cost component of workstatio (3 replies, 11/15/90)
6502 interrupts (4 replies, 11/15/90)
AT&T Crisp (2 replies, 11/15/90)
"Rumours" from BYTE - November 1990 (3 replies, 11/16/90)
Looking for Busses (0 replies, 11/16/90)
humanitarian request (2 replies, 11/16/90)
In defense of the TI9900 (1 reply, 11/16/90)
Killer Micro Question vs. mainframes (1 reply, 11/16/90)
Reminder---1991 ISCA paper submission due real soon (0 replies, 11/16/90)
The CPU with 3 brains (16 replies, 11/16/90)
Hardware C (0 replies, 11/16/90)
Plessey 250 (0 replies, 11/16/90)
Zilog's mnemonics; there's more between heaven and earth ... (0 replies, 11/16/90)
Hypercube research on Information Retrieval (0 replies, 11/16/90)
Letterman's top ten (2 replies, 11/16/90)
Pointers to hyper-cube info (0 replies, 11/17/90)
Count Zero Interrupt (10 replies, 11/17/90)
hi-res monitors (4 replies, 11/17/90)
Useful? (4 replies, 11/17/90)
hi-res monitor cost (0 replies, 11/17/90)
R3000A question ??? (6 replies, 11/17/90)
Beyond these shores - Ease - SEZ Yale (0 replies, 11/17/90)
Replacing paper, + other display stuff (0 replies, 11/18/90)
Harrix RTX bites the dust? (3 replies, 11/18/90)
Zilog's mnemonics; a boon to programmers (6 replies, 11/18/90)
Intel bugs / bugged by Intel : (39 replies, 11/19/90)
Hardware Support for DPMI in the 586 (2 replies, 11/19/90)
68K sources (0 replies, 11/19/90)
Costs of High-resolution graphical displays (8 replies, 11/19/90)
OS cost component of workstation (36 replies, 11/20/90)
Benchmark performance ratios (2 replies, 11/20/90)
Disk Seek Time Measurements (0 replies, 11/20/90)
Graphics Primitives (2 replies, 11/21/90)
Smart I-cache? And separate R/W D-cache (1 reply, 11/21/90)
Faculty Positions (0 replies, 11/21/90)
Hennessy and Patterson (4 replies, 11/22/90)
Porting OSes (16 replies, 11/22/90)
Top Ten Computer Architectures (11 replies, 11/24/90)
P1754 (5 replies, 11/26/90)
CALL FOR VOTES: comp.lang.vhdl (1 reply, 11/26/90)
Paperless Office (1 reply, 11/26/90)
Object oriented architectures (2 replies, 11/27/90)
UNIX (14 replies, 11/27/90)
Plessy 250 (4 replies, 11/27/90)
In What Sense is Sun the "First" Open Systems Manufacturer? (10 replies, 11/27/90)
Motive and Open Systems (0 replies, 11/27/90)
Object-Oriented Procedure Call (3 replies, 11/27/90)
VAX and VMS development (5 replies, 11/27/90)
Request for SPARC info/interpreter (0 replies, 11/28/90)
Sun stuffs their own boards! (0 replies, 11/28/90)
denormalized numbers (0 replies, 11/29/90)
Alternative mnemonics for 8086/8080/Z80 (2 replies, 11/29/90)
The CPU with 3 brains---486 compatibility with 8008 (23 replies, 11/29/90)
Resolution, etc. (14 replies, 11/29/90)
DeNorms (3 replies, 11/30/90)
33 MHz 486 Speed (1 reply, 11/30/90)
page fault handling on the 80386 (2 replies, 11/30/90)
FORTH ENTINGES/ APL 32 bit (0 replies, 11/30/90)
Floating-point formats (3 replies, 12/01/90)
Denorms, Infs, and NaNs (1 reply, 12/01/90)
Division by zero (0 replies, 12/01/90)
True 46 Bit Addressing with 586? (6 replies, 12/01/90)
Any Valid PC Benchmark Software Available? (0 replies, 12/01/90)
pointers to vhdl software (0 replies, 12/01/90)
Polonium-Powered Parallel Processor (0 replies, 12/02/90)
Physical Design Workshop II (0 replies, 12/02/90)
Intel and Antitrust (1 reply, 12/02/90)
Registration Form and Advance Program for the second IEEE Symposium on Parallel and Distributed Processing (1 reply, 12/03/90)
Vote results: comp.research.japan (0 replies, 12/03/90)
Real 46 Bit Addressing in the 386/486!!! (2 replies, 12/03/90)
Joint Venture Announcement - 2 press releases (0 replies, 12/03/90)
Is programming still allowed? (5 replies, 12/03/90)
Request: Vector machine address traces (0 replies, 12/04/90)
an amusing development (1 reply, 12/04/90)
Looking for LINPACK Source (0 replies, 12/04/90)
i432 doc? (1 reply, 12/04/90)
Run-time object analysis (0 replies, 12/05/90)
Phillips (0 replies, 12/05/90)
Branch Target Caches (1 reply, 12/05/90)
Help with new HITACHI product (0 replies, 12/05/90)
CD-ROM software distribution... (2 replies, 12/05/90)
vaxocentrism -- please help me define it for the Jargon File (0 replies, 12/06/90)
uSystem Version 4.3 (0 replies, 12/06/90)
Alignment on RS/6000 (18 replies, 12/07/90)
resolution & arch. dates (0 replies, 12/07/90)
Help with new HITACHI product - SUMMARY of the information (0 replies, 12/07/90)
Request for MIPS info/interpreter (4 replies, 12/08/90)
Handling folders on Mac (1 reply, 12/08/90)
Horsepower Needed for MS-DOSREAD/NEW/FOLLOWUP (1 reply, 12/08/90)
Instruction Frequency (0 replies, 12/09/90)
Sun's Competitive Strategy (47 replies, 12/09/90)
Why my stack grew up and this was wrong (2 replies, 12/09/90)
Upcoming Jargon File 2.2.1 release (0 replies, 12/10/90)
READ ME --> comp.arch appearing in Sigarch's CAN (0 replies, 12/10/90)
Horsepower Needed for MS-DOS (2 replies, 12/10/90)
CD-ROM documents (46 replies, 12/11/90)
IO buses, memory waste (0 replies, 12/11/90)
68020 Simulator Wanted (0 replies, 12/11/90)
Required MIPS (1 reply, 12/11/90)
Echelon's LON (0 replies, 12/12/90)
multiarchitecture chips (1 reply, 12/12/90)
Common Reference Architecture (0 replies, 12/12/90)
NuBus popularity (1 reply, 12/13/90)
Endot's (0 replies, 12/13/90)
Optimal Computer Architectures (18 replies, 12/13/90)
RISCizing a CISC processor (14 replies, 12/14/90)
HDLs (0 replies, 12/14/90)
OS/2 may not be dead, but is comp.arch? (0 replies, 12/14/90)
Raw power and user interfaces (1 reply, 12/14/90)
IO buses (2 replies, 12/14/90)
ACE Hardware Description Language (0 replies, 12/14/90)
Bus specifications (1 reply, 12/15/90)
Delivering Power (1 reply, 12/15/90)
Self Modifying Code, was: m88200 cache flushes on DG Aviion (0 replies, 12/15/90)
Killer Micro Question (19 replies, 12/15/90)
Error rates (1 reply, 12/16/90)
The Jargon File -- version 2.2.1 has been posted... (0 replies, 12/16/90)
Bus specifications, and IEEE P1596 SCI (0 replies, 12/17/90)
I cache/D cache (2 replies, 12/18/90)
Host--network interface architecture (1 reply, 12/18/90)
I-cache flush for SMC (1 reply, 12/18/90)
Why do RISCs use (9 replies, 12/18/90)
PW review of IBM workstation (2 replies, 12/18/90)
synchronisation of the memory interface for the ARM2 (0 replies, 12/19/90)
m88200 cache flushes on DG Aviion (10 replies, 12/19/90)
The term Bug (13 replies, 12/20/90)
486 and FPUs (2 replies, 12/20/90)
GIPS? --> BIPS! (6 replies, 12/20/90)
VM used for filesystems (1 reply, 12/22/90)
Sun Viking chip (4 replies, 12/22/90)
Intel graphics chip (7 replies, 12/22/90)
Sun Rivals Blast SPARCstation 2 in Unix Today! (1 reply, 12/22/90)
The Computer Museum Annual Fund (0 replies, 12/23/90)
ECL SPARC and FPS (0 replies, 12/24/90)
ECL SPARCs and FPS (0 replies, 12/24/90)
gcc and 80386 code (0 replies, 12/24/90)
The old, tired tirade on "more registers" (0 replies, 12/26/90)
further progress on benchmarks (0 replies, 12/26/90)
Undetected error rates, high capacity storage (1 reply, 12/26/90)
ECL and neo-ECL (0 replies, 12/26/90)
MICRO-24; Call for Papers & Participation (0 replies, 12/27/90)
more register flames (2 replies, 12/27/90)
IBM 7094 II (9 replies, 12/27/90)
Call for comments/opinions on the future of GIS software (0 replies, 12/28/90)
What is "Dhrystone"? (1 reply, 12/29/90)
Icache flushes, self-modifying code and multiprocessors (1 reply, 12/29/90)
Newly announced Intel chip running at 100 Mhz? (6 replies, 12/30/90)
Dhrystone/SPEC Correlational Analysis? (3 replies, 01/01/91)
Video controller chip handling overlapping windows (0 replies, 01/01/91)
New Microprocessors Expected in 1991 (1 reply, 01/02/91)
Newly announced Intel chip running (0 replies, 01/03/91)
indirection: who said this? (1 reply, 01/03/91)
reliable/reproduceable benchmarks on SGI MIPS box (7 replies, 01/03/91)
Cambridge HOL System - 5-day Intensive Course (0 replies, 01/04/91)
CRASHME.C, test your hardware and software robustness (0 replies, 01/04/91)
database engines (0 replies, 01/04/91)
CD-ROM II standard? (3 replies, 01/05/91)
DVI (0 replies, 01/06/91)
References on asynchronous design (0 replies, 01/07/91)
Display resolution (1 reply, 01/07/91)
newsgroup for VHDL (0 replies, 01/07/91)
I always thought there was something burning in that computer... (1 reply, 01/07/91)
Futurebus (6 replies, 01/07/91)
tech report advertisment (0 replies, 01/08/91)
Number of registers (1 reply, 01/08/91)
more registers for ix86 (1 reply, 01/08/91)
machines with some loadable microcode are easier to fix (17 replies, 01/08/91)
IBM 360 archaeology (0 replies, 01/08/91)
the future of busses (1 reply, 01/08/91)
AS/400 book (0 replies, 01/09/91)
Terraplex MISC (2 replies, 01/09/91)
registerless architectures (0 replies, 01/09/91)
why is 33 MHz a popular number? (20 replies, 01/09/91)
registerless architecture (26 replies, 01/09/91)
Good books (2 replies, 01/09/91)
Totally asynchronous computers (7 replies, 01/09/91)
more registers for ix86, was: Let's pretend (13 replies, 01/09/91)
Crashing machines with and without microstore, and the IBM AS-400 (2 replies, 01/09/91)
i960 "history" was: more registers for ix86, was: Let's pretend (0 replies, 01/09/91)
ECL 88k, an old posting (1 reply, 01/10/91)
lots of processors on single RAM (0 replies, 01/10/91)
Number of registers, MIPS, GNU cc (2 replies, 01/10/91)
Single user OSs (1 reply, 01/10/91)
Intel's 386 Simulator (0 replies, 01/10/91)
Asynchronous architectures (0 replies, 01/10/91)
FGCS '92 --- Call for Papers (0 replies, 01/10/91)
Call for Attendence: Int Symp on SM Multiprocessing, Tokyo (0 replies, 01/10/91)
Pr.Lang/OS/CPU Design Philosophy; WAS: How wrong is MS-DOS? (0 replies, 01/10/91)
variability in benchmark results (0 replies, 01/11/91)
Need info on HP 1818-2500 uP (0 replies, 01/11/91)
Seeking suggested references (0 replies, 01/11/91)
Information on the DIXIE simulator (0 replies, 01/12/91)
SUMMARY: C compilers for 1750A (0 replies, 01/12/91)
How about CACHE based registers, was: more registers for ix86 (3 replies, 01/13/91)
Advice on understanding PC architecture... (0 replies, 01/13/91)
New SparcStation (17 replies, 01/13/91)
More Register vs. cache (0 replies, 01/13/91)
The Future of Buses (19 replies, 01/14/91)
GREP vs. REGEX (0 replies, 01/15/91)
Take this thread and move it (0 replies, 01/15/91)
fff (0 replies, 01/15/91)
OS/2 is dead? (38 replies, 01/15/91)
Stack Cache with O/S driven copyback ? (2 replies, 01/16/91)
What constitutes a good OS? (3 replies, 01/16/91)
Register Count (18 replies, 01/16/91)
DOS and UNIX (0 replies, 01/16/91)
Sun != Open Archtecture (31 replies, 01/17/91)
It's "Sun Microsystems, not "SUN Microsystems" (0 replies, 01/17/91)
The Russians are coming (1 reply, 01/18/91)
Information on the PIXIE Instruction Simulator (2 replies, 01/18/91)
What's Wrong with MS-DOS (0 replies, 01/18/91)
How wrong is MS-DOS? (71 replies, 01/19/91)
Hardware Equivalent of a Timing Loop (0 replies, 01/19/91)
Reverse map MMU with remappable segments (0 replies, 01/20/91)
IBM RS6000 (14 replies, 01/21/91)
Help: references for memory alignment schemes (0 replies, 01/21/91)
Caches (12 replies, 01/22/91)
UNIX mind-set -> OK, OK! (24 replies, 01/22/91)
MS-DOS OS "architecture" (1 reply, 01/22/91)
Source for 8085 simulator? (0 replies, 01/22/91)
UNIX mind-set (30 replies, 01/22/91)
Superscalar and dataflow (1 reply, 01/22/91)
future globs (0 replies, 01/22/91)
globbing furniture - only brilliant followups please! (0 replies, 01/23/91)
68xxx memory addressing (4 replies, 01/23/91)
rs/6000 pending STF queue (0 replies, 01/23/91)
Electronic weapons -- uP of choice? (4 replies, 01/23/91)
~8-job "knee" in response curves on Suns (16 replies, 01/23/91)
Registers on critical path (0 replies, 01/23/91)
Controller registers vs. Speculative Execution (6 replies, 01/23/91)
loop unrolling (6 replies, 01/23/91)
Intel goes to Cal Supreme Court (0 replies, 01/24/91)
Let's pretend (59 replies, 01/24/91)
Quote from new book (3 replies, 01/25/91)
code reorganization for locality (0 replies, 01/25/91)
SunMMU history (3 replies, 01/25/91)
C/C++ compilers for 1750A? (0 replies, 01/25/91)
3 research posts in comp.arch+comp.ai @ Manchester University, UK (0 replies, 01/25/91)
you'll never need 64-bit hardware addressing (0 replies, 01/26/91)
data-dependent cache misses & gc's (0 replies, 01/26/91)
68k simulator (0 replies, 01/26/91)
What were real machines which helped Turing? (7 replies, 01/26/91)
Asynchronous Microprocessors (3 replies, 01/26/91)
Moto 68451 (4 replies, 01/27/91)
File Changes (0 replies, 01/28/91)
Information needed (0 replies, 01/28/91)
Opinions on Hyperstone ? (3 replies, 01/30/91)
OS Disk services, (0 replies, 01/30/91)
HP 9000/700 "Snake" workstations. (0 replies, 01/30/91)
Whole file caching (0 replies, 01/31/91)
Dartmouth BASIC (0 replies, 01/31/91)
A step ahead of IBM (2 replies, 01/31/91)
SCSI device performance for my VAX? (0 replies, 01/31/91)
Tomasulo (1 reply, 01/31/91)
One obvious reference for coloring and registers (2 replies, 02/01/91)
One step ahead of IBM (0 replies, 02/01/91)
Slow X on IBM RS6000? (4 replies, 02/01/91)
Unix made easy (7 replies, 02/02/91)
RS/6000 cache question; OS implications (0 replies, 02/02/91)
RIOS MMU/X performance, Mach VM. (0 replies, 02/02/91)
To Andras Kovacs (0 replies, 02/04/91)
Bignums, Rationals, Incremental gaussian elimination & simplex (0 replies, 02/04/91)
summer internships (0 replies, 02/05/91)
Symposium on Experiences with Distributed and Multiprocessor Systems (0 replies, 02/05/91)
register access time critical? (2 replies, 02/05/91)
R4000 details????? (5 replies, 02/06/91)
Info on GE-635 (12 replies, 02/06/91)
ISCAS '85 Benchmark Circuits (0 replies, 02/06/91)
Scoreboarding for Superscalar (0 replies, 02/06/91)
THIS DOES NOT BELONG TO COMP.ARCH (0 replies, 02/06/91)
Restarting 'core' files (1 reply, 02/06/91)
cycle counts; was Re: R4000 details????? (0 replies, 02/06/91)
Memory boards and data space (1 reply, 02/06/91)
RS/6000 cache (0 replies, 02/07/91)
Sun bogosities, including MMU thrashing (26 replies, 02/07/91)
Superscalar architectures (0 replies, 02/07/91)
Reed Solomon Code code (2 replies, 02/08/91)
A (9 replies, 02/08/91)
ASPLOS-IV Advance Program (0 replies, 02/08/91)
IBM S/360-95 Re: R4000 "announcement" (1 reply, 02/09/91)
Pseudo-random generation (1 reply, 02/09/91)
Real Time/Cache (17 replies, 02/09/91)
flamage in comp.arch (0 replies, 02/09/91)
File and other disk caches (4 replies, 02/09/91)
Synchronization Survey (2 replies, 02/09/91)
special purpose architectures (1 reply, 02/09/91)
Mach 3.0 availability (0 replies, 02/10/91)
Segmented machines and per process memory limits. (6 replies, 02/10/91)
call for iocall times (1 reply, 02/10/91)
Kneejerk answers to Herman (1 reply, 02/11/91)
68300 speed request (1 reply, 02/11/91)
MP-DOS (0 replies, 02/11/91)
68k emulator (0 replies, 02/11/91)
Jovial vs. CMS II (1 reply, 02/11/91)
How to post Hyperstone info ? (0 replies, 02/11/91)
80-bit IEEE FP (0 replies, 02/12/91)
FLAME ON: Re: Sun bogosities, including MMU thrashing (2 replies, 02/12/91)
File caching (1 reply, 02/12/91)
Help (1 reply, 02/12/91)
Async system interface (4 replies, 02/12/91)
questions regarding schematics in i860 hardware manual. (0 replies, 02/12/91)
Jovial (8 replies, 02/13/91)
Vector processors, i860 (22 replies, 02/13/91)
Real-Time Cache (0 replies, 02/13/91)
Questions regarding missing schematics in i860 hardware manual. (0 replies, 02/13/91)
FileSystem references wanted (1 reply, 02/13/91)
What you need for crash recovery (3 replies, 02/13/91)
integer multiplies on a Sparc (2 replies, 02/13/91)
370 channels and tape drives (1 reply, 02/14/91)
Page size and linkers (25 replies, 02/14/91)
Supercomputing Debugging Workshop '91 (0 replies, 02/14/91)
A long treatise on efficient IO architectures (0 replies, 02/14/91)
A Fast Memory Architecture (7 replies, 02/15/91)
How big is 2^64? (0 replies, 02/15/91)
On-Chip Cache Survey (16 replies, 02/15/91)
Forth Microprocessors (1 reply, 02/15/91)
The killer business application (1 reply, 02/15/91)
R4000 vs. superpipelining (0 replies, 02/16/91)
BCD (0 replies, 02/16/91)
help me recapture old thread (0 replies, 02/16/91)
<<>> HELP! - AES/EBU formating <<>> (0 replies, 02/18/91)
H1 TRANSPUTER DISCLOSURE (0 replies, 02/19/91)
i386 SL (0 replies, 02/19/91)
Ignorance speaks loudest (38 replies, 02/19/91)
Computers for users not programmers (104 replies, 02/19/91)
4T cache cells? (4 replies, 02/19/91)
Whose code should we break? (0 replies, 02/20/91)
VLIW (17 replies, 02/20/91)
RISC reaching its limits?!? (19 replies, 02/20/91)
CALL FOR PARTICIPATION: Hot Chips Symposium III (0 replies, 02/21/91)
Swordfish: compatible with ?? (2 replies, 02/21/91)
MIPS, Compaq and Microsoft in bed - NYT story (23 replies, 02/21/91)
R4000 "announcement" (12 replies, 02/21/91)
Intel and Sun: from a MBA viewpoint (4 replies, 02/21/91)
Swizzling (7 replies, 02/21/91)
What to do on a WS <-> what to do on a SC (0 replies, 02/21/91)
64-bit addressing (6 replies, 02/22/91)
IEE754 floating point `rationale': Summary (0 replies, 02/22/91)
64 bit C (4 replies, 02/22/91)
R4000 - compatibilty questions (3 replies, 02/22/91)
National Semiconductor's Swordfish (1 reply, 02/22/91)
More 64bits (0 replies, 02/22/91)
Asynchronous I/O on micros (2 replies, 02/22/91)
The Future (0 replies, 02/23/91)
64 bit addresses (8 replies, 02/23/91)
64bits: Area Overhead and Opportunity Costs (3 replies, 02/24/91)
Trigonometric Argument Reduction (0 replies, 02/24/91)
Architectural implications of reference based languages (0 replies, 02/25/91)
64-bits, How many years? ... and filling the whole memory ;-) (1 reply, 02/26/91)
Blackledge & Bolles - "An Educational Bit-Slice" (0 replies, 02/26/91)
Braindamaged architectures (1 reply, 02/26/91)
DFT91 - CALL FOR PAPERS (0 replies, 02/26/91)
Summary on Bignums, Rationals, Incremental gaussian elimination & simplex (0 replies, 02/27/91)
bizarre instructionsexi (0 replies, 02/27/91)
obtaining (0 replies, 02/27/91)
r4000 (9 replies, 02/28/91)
Shared Executables (0 replies, 02/28/91)
module size estimation (0 replies, 02/28/91)
sin (8 replies, 03/01/91)
What the compiler CAN do for you (2 replies, 03/01/91)
Recognizing APL idioms (0 replies, 03/02/91)
standard extensions (28 replies, 03/02/91)
VAX ISP (0 replies, 03/03/91)
estimating layout area of IC function blocks (0 replies, 03/04/91)
Call for Papers - WSI Architectures (0 replies, 03/04/91)
68040 Status (2 replies, 03/05/91)
SPEC, eqntott (0 replies, 03/05/91)
68040 and caches (5 replies, 03/05/91)
how many nfsd's should I run? (2 replies, 03/05/91)
Network file service bogosities (3 replies, 03/05/91)
standard extensions to programming languages (1 reply, 03/05/91)
IDEA `91 Conference (0 replies, 03/05/91)
To inline or not to inline (2 replies, 03/05/91)
Instruction Stacks (0 replies, 03/05/91)
Top machine MFLOPs/SPECmarks wanted for comparison with HP9000/700. (2 replies, 03/05/91)
new word order? (9 replies, 03/06/91)
Marginal cache (1 reply, 03/06/91)
National Semiconductor's Swordfish microprocessor (5 replies, 03/06/91)
disk queues of length zero..... or scaling up hurts (0 replies, 03/06/91)
instruction stack (6 replies, 03/07/91)
Getting accounts on the UMIACS Parallel Processing machines (0 replies, 03/07/91)
MICRO-24 (0 replies, 03/07/91)
"typical" R2000 source code needed (0 replies, 03/07/91)
disk queues (0 replies, 03/07/91)
CDC 6600 and TI ASC probably, STAR-100 and ASC (0 replies, 03/08/91)
new Weitek chip rumor (0 replies, 03/08/91)
Need info on SPARC memory behavior (0 replies, 03/08/91)
bizarre instructions really subroutine overhead (1 reply, 03/08/91)
bizarre instructions (53 replies, 03/08/91)
disk queues of length zero..... (3 replies, 03/08/91)
The merits of FCFS for file servers (3 replies, 03/08/91)
68040 Status - SPEC table with missing line added (1 reply, 03/08/91)
TRANSPUTING '91 (1 reply, 03/09/91)
1991 IEEE Symp on Parallel & Distributed Processing (0 replies, 03/09/91)
What the compiler won't do you for you (20 replies, 03/09/91)
SPEC table (0 replies, 03/10/91)
VM Measurement (1 reply, 03/11/91)
STE European Bus Standard (0 replies, 03/11/91)
Jackpot cases (0 replies, 03/12/91)
Vectorizing compilers ILs? (0 replies, 03/12/91)
Return addresses (0 replies, 03/12/91)
CDC 6600 and TI ASC (6 replies, 03/12/91)
first class functions (1 reply, 03/12/91)
Submission for news (0 replies, 03/12/91)
Be Prepared... (34 replies, 03/13/91)
Divide in 1 cycle (9 replies, 03/13/91)
James E. Smith / Norman P. Jouppi (0 replies, 03/14/91)
Looking for timing diagram drawing tool (0 replies, 03/15/91)
massive parallelism, was CDC 6600 and TI ASC (10 replies, 03/15/91)
register save (47 replies, 03/15/91)
36bit (0 replies, 03/15/91)
Faster controllers easier and cheaper than fast CPUs.... (3 replies, 03/15/91)
Jargon File distribution -- policy query (1 reply, 03/15/91)
VRAMS as memory (1 reply, 03/15/91)
National's Swordfish - request (0 replies, 03/15/91)
Unusual instructions and constructions (13 replies, 03/16/91)
Instruction scheduling an executable (0 replies, 03/16/91)
NAS Benchmarks on the CM-2 (0 replies, 03/16/91)
R4000 data cache stalls (1 reply, 03/16/91)
Tahoe calls (0 replies, 03/17/91)
Globbing (30 replies, 03/18/91)
shell architecture (33 replies, 03/18/91)
Unusual instructions and constructions - words (1 reply, 03/19/91)
Price/Performance figures for Number-Crunching (0 replies, 03/19/91)
Synthetic Life (0 replies, 03/19/91)
Offloading I/O [was:Incremental sync (3 replies, 03/19/91)
IBM RS/6000 (7 replies, 03/19/91)
Synthetic Life followup: Artificial Life mailing list (0 replies, 03/19/91)
ASPLOS-IV Bonus SCI tutorial (0 replies, 03/20/91)
Sixth Distributed Memory Computing Conference (0 replies, 03/20/91)
DhropStone (0 replies, 03/20/91)
Cache Measurement (1 reply, 03/21/91)
Access to SPEC-Benchmarks, Comp.arch archive (1 reply, 03/21/91)
Obit: Sid Fernbach (0 replies, 03/21/91)
A SPARC architecture manual. (6 replies, 03/21/91)
Am386 release? (15 replies, 03/22/91)
48-bit computers (13 replies, 03/22/91)
PgC 7600 (0 replies, 03/22/91)
Log Library - How is it done in the library code? (0 replies, 03/22/91)
64-bits, How many years? (20 replies, 03/22/91)
Smart IO controllers - my thoughts (1 reply, 03/22/91)
DSP benchmarks ? (0 replies, 03/23/91)
In Defense of Decstations (0 replies, 03/23/91)
The Jargon File version 2.8.1, 22 MAR 1991 has been released (0 replies, 03/23/91)
Translating 64-bit addresses (36 replies, 03/23/91)
Multis (0 replies, 03/24/91)
Pdp10/Pdp11 Software (0 replies, 03/24/91)
Neural Nets??? (0 replies, 03/25/91)
New SPARC definition (4 replies, 03/25/91)
New SPARC definition, and volatile (0 replies, 03/25/91)
life-time in FIFO-caches and LRU-caches (0 replies, 03/26/91)
Hamming code (6 replies, 03/26/91)
Novice question: measuring speed (22 replies, 03/26/91)
Microcomputer Bus Multiprocessing (8 replies, 03/27/91)
Educational Features of TRANSPUTING '91 (0 replies, 03/27/91)
I/O or file system benchmarks (1 reply, 03/27/91)
Call for Papers (2 replies, 03/27/91)
PDP-10 (4 replies, 03/27/91)
cache pre-load/no-load instructions (13 replies, 03/27/91)
Time Line for new chip intro desired. (0 replies, 03/27/91)
Branch Delay Slots (0 replies, 03/28/91)
Interlocked Pipelines - basic questions (3 replies, 03/28/91)
Data General NEW AVIION machine (19 replies, 03/29/91)
Von Neumann Architectures (2 replies, 03/29/91)
Second-generation RISC (11 replies, 03/29/91)
More von N (0 replies, 03/29/91)
Snake (15 replies, 03/30/91)
Instruction set details for RS/6000? (0 replies, 03/30/91)
Coprocessors (6 replies, 03/31/91)
CFP - HICSS 25 High performance Special Purpose Accelerators (0 replies, 04/02/91)
SPECmarks/MHz (2 replies, 04/02/91)
how big are the queues on the SPARC floating point units? (3 replies, 04/03/91)
portability problems... (0 replies, 04/03/91)
CFP SI of IEEE Trans. on Computers on Fault-Tolerant Computing (0 replies, 04/03/91)
SPEC/MHZ (0 replies, 04/03/91)
porting to 64-bits (0 replies, 04/04/91)
Branch Delay Slots and Main Memory (1 reply, 04/04/91)
Unix block I/O (0 replies, 04/04/91)
Question on Latest HP Apollo Workstations. (0 replies, 04/04/91)
Memory hierarchy (9 replies, 04/04/91)
Looking for the right processor (0 replies, 04/05/91)
Coprocessors - Business? (8 replies, 04/05/91)
Workshop Announcement (0 replies, 04/05/91)
Invited Speakers at TRANSPUTING '91 (0 replies, 04/05/91)
Backplane Buses (2 replies, 04/05/91)
Secondary cache (0 replies, 04/05/91)
Updated Program for 18th ISCA (0 replies, 04/06/91)
$/CPUmark is a worthless measure (5 replies, 04/06/91)
cycles per instruction (0 replies, 04/06/91)
CFP: HICSS - 25 (0 replies, 04/06/91)
SPARC specs (4 replies, 04/06/91)
CAM-7 (1 reply, 04/07/91)
memory management implementations (3 replies, 04/07/91)
CFP: Systems Design Synthesis Workshop (0 replies, 04/08/91)
EISA SCSI? (2 replies, 04/09/91)
Info on RAID, Datadeclustering, Disk Synchronization (0 replies, 04/09/91)
Optical Tape (2 replies, 04/09/91)
Algol68 (21 replies, 04/10/91)
More Snake bytes. (16 replies, 04/10/91)
TRANSPUTING '91 - daily rates and last chance for accommodation (0 replies, 04/10/91)
I'm seeking some information about HardwareC (0 replies, 04/10/91)
Segmented Architecture (0 replies, 04/10/91)
Question about Patterson/Hennessey simulator (0 replies, 04/10/91)
Anyone know about this 200 MIPS chip? (2 replies, 04/11/91)
Tools for Computer Architecture Simulation (0 replies, 04/11/91)
Info on HYPERSTONE comming here (1 reply, 04/12/91)
i860 Question on Buffered Loads/Stores (0 replies, 04/13/91)
Electronic books (1 reply, 04/15/91)
Low End NeXTs (7 replies, 04/15/91)
Suggestions please -- debugging multi-threaded programs (0 replies, 04/15/91)
Optical Interconnect (7 replies, 04/15/91)
Compilers & SPECmarks... (12 replies, 04/16/91)
Bitfield instructions (0 replies, 04/16/91)
What about loop instructions? (1 reply, 04/16/91)
How to REALLY compute a SPECmark (0 replies, 04/16/91)
EISA card development for the Snake? (1 reply, 04/16/91)
Engineer Needed - Architect, OpenLook, X (0 replies, 04/16/91)
Optical Interconnect could be rather easy! (3 replies, 04/16/91)
process migration - status and availability (0 replies, 04/17/91)
Macintosh MIPS,MFLOPS, and SPECmarks (2 replies, 04/17/91)
Wanted: DEC 10/20 Stuff/Emulators (0 replies, 04/17/91)
Dataflow Architectures and Languages Course Announcement (0 replies, 04/18/91)
Instruction Scheduling (25 replies, 04/18/91)
Dataflow Architectures and Languages Summer Course (0 replies, 04/18/91)
CFP: Int'l Conference on Fifth Generation Compute (0 replies, 04/18/91)
Summary -- multi-thread debugging (0 replies, 04/19/91)
Bitfield instructions, HP & 88K (0 replies, 04/19/91)
HP Technology conference impressions (0 replies, 04/19/91)
Bitfield and loop instructions--a good idea? (6 replies, 04/20/91)
Microprocessor Forum Announcement (0 replies, 04/20/91)
Incremental sync (37 replies, 04/21/91)
Networking for Distributed Computing (7 replies, 04/21/91)
Dynamic Display Architecture (9 replies, 04/21/91)
Dec-10/20 emulator (0 replies, 04/21/91)
Lost pages in swapfile ? (2 replies, 04/22/91)
Adding fire to the segmentation flamefest... (9 replies, 04/22/91)
Fidonet strikes again (0 replies, 04/22/91)
The return of the ETA (0 replies, 04/23/91)
Wanted DEC-10/20 stuff, and emulator (3 replies, 04/23/91)
Optimising C compiler question (16 replies, 04/23/91)
Floating Point Risc (8 replies, 04/23/91)
Sun4 caches? (1 reply, 04/23/91)
Segmented Architectures (86 replies, 04/23/91)
RISC integer multiply/divide (16 replies, 04/23/91)
Caching the frame buffer (0 replies, 04/23/91)
Living With Old Baggage (3 replies, 04/24/91)
overview of HP-PA Bitfield insts. (6 replies, 04/24/91)
neural network reprints available (0 replies, 04/24/91)
Wet Dream or ... (7 replies, 04/24/91)
Compare and swap vs. test and set (0 replies, 04/24/91)
Query: DLX software for Hennessy/Patterson (0 replies, 04/24/91)
optional uncached load/store (1 reply, 04/24/91)
Wanted: Dec-20 Parts (1 reply, 04/24/91)
SPARC implementation or architecture (13 replies, 04/25/91)
RISC Compare & Swap (1 reply, 04/25/91)
Help with Hennessy&Patterson's Book Software (0 replies, 04/25/91)
more cache/uncached ld/st (2 replies, 04/25/91)
Free APLOS proceedings (1 reply, 04/25/91)
Solbourne (1 reply, 04/25/91)
PC-world video frame buffers (0 replies, 04/26/91)
Virtual Address Limits on Suns (0 replies, 04/26/91)
Magnum Workstation and Cached Framebuffers (1 reply, 04/26/91)
Bitfield instructions--a good idea? (31 replies, 04/26/91)
Snakes... HP process technology (1 reply, 04/26/91)
optimizer compilers (0 replies, 04/26/91)
performance vector approaches (0 replies, 04/27/91)
anybody *need* a Dec-10/20? (0 replies, 04/27/91)
Multiple data buses (0 replies, 04/27/91)
Reference wanted on inverted page tables (0 replies, 04/29/91)
Snakebytes (34 replies, 04/29/91)
CFP: System Evaluation and Assessment Technology Workshop (0 replies, 04/30/91)
10th Symposium on Computer Arithmetic (1 reply, 04/30/91)
SPARC tagged data (3 replies, 04/30/91)
A short note on posting to comp.arch (3 replies, 05/01/91)
Write-back controllers (1 reply, 05/01/91)
Cordic Math Algorithms (2 replies, 05/02/91)
Video implementation on NeXTstation color (1 reply, 05/02/91)
DEC3000/5000 memory-interface (0 replies, 05/02/91)
memory architectures? (0 replies, 05/03/91)
Cray virtual memory quote (0 replies, 05/03/91)
Compilers, architecture, efficiency, and nonsense (0 replies, 05/03/91)
1992 (1 reply, 05/03/91)
database coprocessors (0 replies, 05/03/91)
GaAs RISCs (1 reply, 05/04/91)
RISC & CISC; also ANSWER TO cfc1 question (0 replies, 05/04/91)
How many internal devices to be installed in a CUBE? (1 reply, 05/05/91)
Small signal swings for high speed cheap SCI links (0 replies, 05/05/91)
June SCI meeting in Geneva (0 replies, 05/05/91)
RISC & CISC; (0 replies, 05/05/91)
New Book Announcement: The Art of Computer Systems Performance Analysis (0 replies, 05/05/91)
If the Network is the Computer, we're in trouble (0 replies, 05/06/91)
Oh stop it! (0 replies, 05/06/91)
How do you make poly-silicon ingots? (1 reply, 05/06/91)
FSF work on a GNU OS (0 replies, 05/06/91)
H1 details? (8 replies, 05/06/91)
Mass produced custom chips (18 replies, 05/06/91)
Compilers, architecture, efficiency, and HR (4 replies, 05/07/91)
BSD virtual memory mngmt algorithm. Was: Performance Tuning Ultrix 4.1 (0 replies, 05/07/91)
simm pinout (0 replies, 05/08/91)
INMOS... (1 reply, 05/08/91)
What does VME stand for? (20 replies, 05/09/91)
Avatex modem -> setting switches (2 replies, 05/09/91)
2.5 Addr Archs (1 reply, 05/09/91)
RISC and fast I/O (0 replies, 05/10/91)
Cache Preload (0 replies, 05/10/91)
T9000 (1 reply, 05/10/91)
IBM-PC screen driver (0 replies, 05/11/91)
Scalar vs Superscalar (5 replies, 05/11/91)
Distance to next bit (0 replies, 05/12/91)
Clarification on 3 Addr vs 2 Addr Archs (7 replies, 05/12/91)
Thanks, enough already. (0 replies, 05/12/91)
Vector vs Cache/Superscalar (19 replies, 05/12/91)
Lead time to a working system. (2 replies, 05/12/91)
Heat problem on IIT 387 compatable. What now? (0 replies, 05/12/91)
Compilers, architecture, and efficiency (13 replies, 05/13/91)
generating random numbers (1 reply, 05/13/91)
Memory access functional units (0 replies, 05/13/91)
>>>>> endian etc... (0 replies, 05/13/91)
Creeping Featureism (0 replies, 05/13/91)
HP700/Snake details (4 replies, 05/13/91)
MP floating point (0 replies, 05/13/91)
Books on INMOS Transputer... (0 replies, 05/14/91)
HP-PA and CISC emulation (2 replies, 05/14/91)
Memory hierarchies (2 replies, 05/14/91)
Control hardware for pipelined RISC processors (0 replies, 05/14/91)
Fujitsu linear recurrence vector instruction (0 replies, 05/14/91)
how to compute exp (0 replies, 05/14/91)
Extensible languages (0 replies, 05/14/91)
Call for paper - JPDC (0 replies, 05/14/91)
RS6000 dynamic instruction counting (1 reply, 05/14/91)
MIPS endian (0 replies, 05/15/91)
dynamic instruction counting (0 replies, 05/15/91)
Can old architectures run fast? (14 replies, 05/15/91)
Hardware considerations (2 replies, 05/15/91)
Voice mail technology... (0 replies, 05/15/91)
SEDMS II Proceedings Now Available (0 replies, 05/16/91)
bi-endian environments (7 replies, 05/16/91)
RT-level simulator wanted (0 replies, 05/16/91)
argument reduction in elementary transcendental functions (0 replies, 05/16/91)
Endianess again (1 reply, 05/16/91)
cache benchmarks (0 replies, 05/16/91)
looking for fifo source (0 replies, 05/17/91)
Convex C3 (1 reply, 05/17/91)
Three Address vs Two Address Architectures (4 replies, 05/17/91)
NCR 3600 (0 replies, 05/17/91)
Compilers and efficiency (73 replies, 05/17/91)
skip instructions (22 replies, 05/17/91)
Loop instructions (16 replies, 05/17/91)
communication between fixed and float units (0 replies, 05/17/91)
float/float = integer, remainder (7 replies, 05/17/91)
condition codes (6 replies, 05/17/91)
Repost: CFP - Systems Design Synthesis Workshop (0 replies, 05/17/91)
RISC vs. CISC -- SPECmarks (51 replies, 05/18/91)
Memory speed, why so slow? (7 replies, 05/18/91)
Book reviewers for computer organization needed (0 replies, 05/18/91)
Endianess resolved, by one who knows. (0 replies, 05/18/91)
Info Request (0 replies, 05/19/91)
Next and NuBus (0 replies, 05/19/91)
What's in the '586 (1 reply, 05/20/91)
endian etc (10 replies, 05/20/91)
HP Snakes Networking (0 replies, 05/20/91)
VISC - speeding up moto cisc mpu's? (1 reply, 05/20/91)
New Moto chips (18 replies, 05/21/91)
un-normalized floating point etc (1 reply, 05/21/91)
Frequency of elementary functions (5 replies, 05/21/91)
Fast I/O (4 replies, 05/22/91)
Comprehensive i860 performance report (1 reply, 05/22/91)
More Small Benchmark Results (0 replies, 05/22/91)
Interrupt handler for the i860 (2 replies, 05/22/91)
FPCA 91 Advance Program (0 replies, 05/22/91)
Newbie type questions (0 replies, 05/22/91)
EE Times article "Intel's CPU wars: the 32-bit struggle for succession" (0 replies, 05/23/91)
ieee floating standard (4 replies, 05/23/91)
CISC MIPS/MHz Again (4 replies, 05/24/91)
bobstone measurements (3 replies, 05/24/91)
Teraplex MISC: what does (0 replies, 05/24/91)
OOOPS, forget the vector bobstone (0 replies, 05/24/91)
Amdahl's Law vs Amdahl/Case Rule (2 replies, 05/24/91)
What does "cascoded" mean? (1 reply, 05/24/91)
Predominance of IEEE 754 floating-point arithmetic? (0 replies, 05/25/91)
Amdahl's Rule (6 replies, 05/25/91)
LOOKING FOR iPSC/2 ARCHITECTURE (0 replies, 05/27/91)
Code to Data ratio (2 replies, 05/28/91)
ACE, buses, and the future of ultrix (8 replies, 05/28/91)
Small Benchmarks (0 replies, 05/28/91)
Atomic operations (15 replies, 05/28/91)
Arithmetic co-processor for Sun 4/75 ? (0 replies, 05/29/91)
Derrick Lehmer - a real computer architect (0 replies, 05/29/91)
FFT for SPARC (1 reply, 05/29/91)
bobstones (0 replies, 05/29/91)
The MIPS EXECUTE instruction (2 replies, 05/29/91)
Mini-CD revisited... (0 replies, 05/29/91)
VAX EDIV remainder (1 reply, 05/29/91)
Will NeXT survive? Grow with the times? (39 replies, 05/29/91)
Image Compression Microcode Architect Wanted (0 replies, 05/29/91)
what if the i860 had vector registers... ? (3 replies, 05/29/91)
Accurate results from FP computation (0 replies, 05/29/91)
MAC/UNIX Questions (0 replies, 05/29/91)
Supporting large files > 2GBytes (0 replies, 05/30/91)
'586 Feature Ideas (1 reply, 05/30/91)
Anything wrong with the i860 (26 replies, 05/30/91)
New 110 MIPS HP Snake at under $10,000. (4 replies, 05/30/91)
What's in the '586?ex (0 replies, 05/31/91)
VISC - A way to speed up moto cisc mpu's? (12 replies, 05/31/91)
errors and error bounds in floating-point arithmetic (1 reply, 05/31/91)
Large Files (5 replies, 05/31/91)
Derrick Lehmer & pseudo random numbers generation (0 replies, 05/31/91)
using those sound chips (0 replies, 05/31/91)
Workstation def (0 replies, 05/31/91)
iWARP notes... it's pretty neat (4 replies, 06/01/91)
A reminder about posting to comp.arch (0 replies, 06/01/91)
What's in the '586? (54 replies, 06/02/91)
Integer/floating (2 replies, 06/02/91)
Intel Touchstone Delta Info (0 replies, 06/02/91)
I/O performance of Intel Touchstone Delta (0 replies, 06/03/91)
Help, architects!!! Tough career decisions in college.... (1 reply, 06/03/91)
68000/10/20 timing data wanted (0 replies, 06/04/91)
Kahaner Report: Cyclic Pipelined Computer and ERATO (0 replies, 06/04/91)
Just an idea for the gang at Intel. (1 reply, 06/04/91)
Touchstone Delta followup (1 reply, 06/04/91)
HOT CHIPS SYMPOSIUM III (2 replies, 06/05/91)
82596CA (1 reply, 06/05/91)
VLIW references (5 replies, 06/05/91)
X windows (0 replies, 06/05/91)
new instructions (39 replies, 06/05/91)
Small Benchmark (8 replies, 06/06/91)
Looking for Used Signatone S250-5" (0 replies, 06/06/91)
2's Logarithms (0 replies, 06/06/91)
LINPACK vs. parallel LINPACK (0 replies, 06/06/91)
X terminals or Dataless for database? (0 replies, 06/06/91)
Futurebus+ (1 reply, 06/07/91)
040 vs 030 SPEC nos. (2 replies, 06/07/91)
Intel sets a trap? (0 replies, 06/07/91)
MIPS 305x (1 reply, 06/07/91)
Info on RAID drives (1 reply, 06/07/91)
Double length Fortran integers (0 replies, 06/08/91)
PC/RT Floating Point (0 replies, 06/08/91)
ACE (27 replies, 06/08/91)
parity is for farmers? (22 replies, 06/09/91)
N11 - i860 XP - some details, who knows more? (1 reply, 06/09/91)
Organization of information (0 replies, 06/09/91)
iWarp Architecture (0 replies, 06/09/91)
Magnetic core switches (0 replies, 06/10/91)
Benchmarking performance vs. robustness (0 replies, 06/10/91)
Position available: Associate Professor of CS, Denmark (0 replies, 06/10/91)
Thinko announcement (2 replies, 06/11/91)
ICPP (0 replies, 06/11/91)
X11r4 availability (2 replies, 06/11/91)
looking for i860 benchmarking report (0 replies, 06/11/91)
BCPL (0 replies, 06/11/91)
IBM floating point using logarithms (2 replies, 06/12/91)
Vax history (0 replies, 06/12/91)
IT'S CM-200!! (0 replies, 06/12/91)
Multiple Register sets (0 replies, 06/13/91)
logarithmic number representation (0 replies, 06/13/91)
IEEE floating point (34 replies, 06/13/91)
Linpack benchmark condition; antipivoting stability (0 replies, 06/13/91)
Massively Parallel LINPACK on the Intel Touchstone Delta machine (10 replies, 06/14/91)
MIPS Simulator (0 replies, 06/14/91)
more Sigma series remembrances (0 replies, 06/14/91)
Moto 88110 ? (1 reply, 06/14/91)
Is double->int slow? (7 replies, 06/14/91)
iWarp Architecture Overview (14 replies, 06/15/91)
VMEbus controller ICs (1 reply, 06/15/91)
MIPS LL & SC instrs (6 replies, 06/15/91)
massive linpack (8 replies, 06/15/91)
Could I get the original '586 posting? (1 reply, 06/15/91)
Pneumatic computers (17 replies, 06/15/91)
call for papers - special issue of VLSI neural networks (0 replies, 06/15/91)
Sales Figures (0 replies, 06/16/91)
test (12 replies, 06/17/91)
UMA NUMA (5 replies, 06/18/91)
isamax and instruction set design, and IEEE interval arith. (0 replies, 06/18/91)
HP PA-RISC Cache Question (4 replies, 06/18/91)
RISC vs CISC (39 replies, 06/18/91)
LL and SC citation? (0 replies, 06/19/91)
Multithreaded Debuggers--Info needed (0 replies, 06/19/91)
Analogies and Performance (0 replies, 06/19/91)
Recent Specmarks, please? (0 replies, 06/19/91)
XDS940 computer (23 replies, 06/19/91)
Animal architecture (1 reply, 06/19/91)
small instructions (17 replies, 06/19/91)
isamax and instruction set design (6 replies, 06/20/91)
Condition number of uniform random matrices; residuals (2 replies, 06/20/91)
More on condition numbers of uniform random matrices, especially Linpack (0 replies, 06/20/91)
Interval Tools (0 replies, 06/20/91)
Can we build computers that build Computers? (7 replies, 06/21/91)
condition numbers of uniform random matrices (0 replies, 06/21/91)
optimization and IEEE arithmetic (0 replies, 06/21/91)
CISC vs. RISC Code Sizes (6 replies, 06/21/91)
INTEL 960MX (0 replies, 06/22/91)
More on Linpack pivoting: isamax and instruction set design (9 replies, 06/22/91)
rounded vs. chopped floating-point arithmetic (1 reply, 06/22/91)
Fault-Tolerant Systems (3 replies, 06/22/91)
Three-Level Metal (5 replies, 06/23/91)
Error magnitude in i860 fp divide. (1 reply, 06/24/91)
"Optimizations" and accuracy (0 replies, 06/24/91)
Address Traces (1 reply, 06/25/91)
Changing IEEE rounding modes on the fly (4 replies, 06/25/91)
Correct? programs (0 replies, 06/25/91)
Active Memory (0 replies, 06/25/91)
Faster busses are hard; can we do wider? (3 replies, 06/26/91)
Implementing Interval Arithmetic with IEEE rounding modes (9 replies, 06/26/91)
Branchless conditionals (7 replies, 06/26/91)
32->64 bit Killer Micros (2 replies, 06/26/91)
References on Compaq's IDA (0 replies, 06/27/91)
Suggestions for SPEC 3.0 CPU Performance Evaluation Suite (4 replies, 06/28/91)
Does any one know where I can get zoo (0 replies, 06/28/91)
What is the ratio of programs sizes CISC versus RISC (13 replies, 06/28/91)
Killer Micro Ensembles (0 replies, 06/28/91)
tenure track faculty position (13 replies, 06/28/91)
** Workstation hardware diagnostics ** (0 replies, 06/28/91)
US Memory supplier (0 replies, 06/29/91)
Information on MC88110 requested (9 replies, 06/29/91)
IEEE arithmetic (88 replies, 06/30/91)
error magnitude in i860 divide - reread the question. (0 replies, 06/30/91)
64 Bit addressing on R4000? (8 replies, 07/01/91)
addressing on Mips (1 reply, 07/01/91)