jangr@microsoft.UUCP (Jan Gray) (01/20/89)
In article <13737@ico.ISC.COM> rcd@ico.ISC.COM (Dick Dunn) writes: >OK, I took two shots (straightening things out on the Colorado-based >companies) - so what's metaflow? (Present or future, high-end or not?) Future, high-end. The Dec. 88 Microprocessor Report has a very interesting report on the Metaflow Sparc implementation. Currently it is "just" a gate-level simulation of the chip set and an RTL sim. of an entire system. They intend to implement it in standard-cell ECL or BiCMOS for late '89. Their claimed performance is "12 times that of the Sun 4/200" which is very good (but not quite so good as it sounds the first time you read it). Their implementation dispatches multiple instructions per cycle. They claim to "virtually eliminate performance loss due to data dependencies" by using very fancy out-of-order execution, invisible registers to hold results that can't yet be written back, scheduling loads ahead of stores, shelving instructions that can't be executed yet (running them later in additional functional units when the instructions' dependencies become available), and using "speculative execution" and branch prediction to eliminate stalling at branch points. The article goes on to describe Metaflow's intentions to do an implementation of the 386. The legal aspects may be even more daunting than the implementation itself! This is one of the directions that future RISC implementations will have to take to keep Joy's law going for a few more years. Very interesting stuff. Perhaps Michael Slater will post the entire article (or perhaps he'd rather you purchased a subscription to his fine newsletter). Jan Gray uunet!microsoft!jangr Microsoft Corp., Redmond Wash. 206-882-8080