jsp@b.gp.cs.cmu.edu (John Pieper) (10/20/88)
Actually, I heard a guy from Motorola talking about their n+1st generation 680X0 machine -- they run an internal clock at 2X the external clock, and play some other tricks to get 14 MIPS effective, 25 MIPS max @ 25 MHz. Seems to me that CISC designers could do this very effectively to get ahead of the RISC types (modulo the design time). BTW, as far as design time goes, you have to take the RISC argument with a grain of salt. the 68030 is only a little different that the 68020, but with technology advances and just a few man-years they more than tripled the speed of the initial 68020 release (in 82?). The 68040 will take the same basic ALU design, and add the FPU. This shouldn't require too much redesign. The point is that a good CISC design can be modified (added to) as quickly as a major redesign of a RISC chip. What really counts is who can sell their instruction set. ----------------------------------- -- ------------------------------------------------------------- John Pieper jsp@n.sp.cs.cmu.edu Computer Science Department Carnegie-Mellon University Pittsburgh, Pa 15213 "Supersonicous Siliconous"? What we need is Warp speed!
bcase@cup.portal.com (Brian bcase Case) (10/21/88)
>680X0 machine -- they run an internal clock at 2X the external clock, and >play some other tricks to get 14 MIPS effective, 25 MIPS max @ 25 MHz. Seems >to me that CISC designers could do this very effectively to get ahead of the >RISC types (modulo the design time). Sigh. Can RISC do this too? Yes. This is an implementation technique, not an inherent advantage. >The 68040 will take the same >basic ALU design, and add the FPU. This shouldn't require too much redesign. >The point is that a good CISC design can be modified (added to) as quickly >as a major redesign of a RISC chip. What really counts is who can sell their >instruction set. The basic ALU design might be preserved, by they are getting the performance they claim by implementing the subset of the 68000 instruction set that are simple with RISC techniques. This does little or nothing for the complex instructions and addressing modes, so they re-write the compilers to use only or mostly the simple instructions. Is this CISC? This is certainly not something that "...shouldn't require too much redesign"! I think the 68040 will be neat. But I wonldn't want to design or pay for it.
mslater@cup.portal.com (Michael MPR Slater) (10/22/88)
I think the 68040 will also be much more heavily pipelined that the 030, so this too implies that it is not a simple redesign of the 020/030. Michael