lamaster@pioneer.arpa (Hugh LaMaster) (05/15/87)
>>(Has anyone ever made a machine the pre-fetches I-cache lines from memory?)
The CDC Cyber 7600 and 176, possibly other later Cybers (865/875),
(7600 designed by Cray, others derived from that design),
all Crays,
the Cyber 205 (entirely different architecture machine from CDC)
and derivative machines (ETA-10),
all had I - cache prefetch.
An earlier machine, the CDC 6600, had instruction STACK (not exactly
a cache) prefetch.
In most of the above instances, two "words" (each word with 2-16
instructions depending on the machine) were prefetched. The technique
has been used on other high performance machines as well. It may have
been used on the IBM 360/91 and 360/195. Anyway, the technique is at
least 23 years old if you count the 6600. It works, too :-)
Instruction prefetch is one of the many performance benefits derived
when you separate the instruction cache and the data cache.
Hugh LaMaster, m/s 233-9, UUCP {seismo,topaz,lll-crg,ucbvax}!
NASA Ames Research Center ames!pioneer!lamaster
Moffett Field, CA 94035 ARPA lamaster@ames-pioneer.arpa
Phone: (415)694-6117 ARPA lamaster@pioneer.arc.nasa.gov
"In order to promise genuine progress, the acronym RISC should stand
for REGULAR (not reduced) instruction set computer." - Wirth
("Any opinions expressed herein are solely the responsibility of the
author and do not represent the opinions of NASA or the U.S. Government")mat@amdahl.amdahl.com (Mike Taylor) (05/15/87)
In article <1551@ames.UUCP>, lamaster@pioneer.arpa (Hugh LaMaster) writes: >>(Has anyone ever made a machine the pre-fetches I-cache lines from memory?) Amdahl machines do both instruction and operand prefetching into the cache. There is also an I-unit instruction queue that prefetches from the cache (a distinct mechanism). -- Mike Taylor ...!{ihnp4,hplabs,amd,sun}!amdahl!mat [ This may not reflect my opinion, let alone anyone else's. ]
kds@mipos3.UUCP (Ken Shoemaker ~) (05/19/87)
In article <1551@ames.UUCP> lamaster@ames-pioneer.arpa (Hugh LaMaster) writes: >Instruction prefetch is one of the many performance benefits derived >when you separate the instruction cache and the data cache. of course, seperating the instruction and data caches is not a necessary condition to allowing instruction prefetch! -- The above views are personal. ...and they whisper and they chatter, but it really doesn't matter. Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California uucp: ...{hplabs|decwrl|amdcad|qantel|pur-ee|scgvaxd|oliveb}!intelca!mipos3!kds csnet/arpanet: kds@mipos3.intel.com