peter@ficc.uu.net (Peter da Silva) (03/23/90)
(for comp.arch folks, Jim is basically saying that the more registers you
have, the better, because it lets you put more variables in registers)
But, Jim, registers aren't free. The more registers you have the more bits
you have to hide in your carefully crafted instruction set to specify
registers. Modern RISC processors have up to 4 arguments to a given
instruction, so even if they're all registers (no mixed-mode instructions)
and you only have 16 registers, that's 16 bits gone right there.
Now, let's add some more bits to specify constants and maybe some addressing
modes, and you can run out of bits pretty quickly. With 64 registers (about
the most I'd expect you to be happy with), and immediate operands that
would leave you with about 5 bits to specify the instruction. Now suppose
you have room on the chip for 512 registers... why *not* use register
windows, or a stack cache, or something similar instead of just making
the instruction wider?
--
_--_|\ `-_-' Peter da Silva. +1 713 274 5180. <peter@ficc.uu.net>.
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voconnordm@CRD.GE.COM (Dennis M. O'Connor) (03/23/90)
peter@ficc (Peter da Silva) writes:
] (for comp.arch folks, Jim is basically saying that the more registers you
] have, the better, because it lets you put more variables in registers)
]
] But, Jim, registers aren't free. The more registers you have the more bits
] you have to hide in your carefully crafted instruction set ...
] ... Now suppose you have room on the chip for 512 registers... why *not*
] use register windows, or a stack cache ... instead of just making the
] instruction wider?
There are of course other costs that come with lots of registers :
Unexpected Context Switch times : goes up, since you have more
CPU state to save. If you know the context switch is coming (like
before a call to a kernal "WAIT_FOR_SIG" entry) you can decrease
this penalty. On some kinds of interrupts, you may not be able to.
Processor Speed : more registers means more loading on the
internal processor busses, and it means these busses are longer.
So you get more capacitance, and higher resistance in the lines.
So your busses get slower. If the busses are not part of a critical
path, you're okay. But eventually, as you add more registers,
your busses will become part of a critical path.
This last effect was a major point of RISC (vs. CISC) design philosophy :
generally, you can't tack more stuff onto a circuit without possibly
slowing it down. So you should be able to show a definate performance
improvement to justify a potential slowing of the clock rate.
Some big-register-set opponents ( big >> 32 ) argue that the supporters
of this idea haven't conclusively demonstrated any such improvement.
--
Dennis O'Connor OCONNORDM@CRD.GE.COM UUNET!CRD.GE.COM!OCONNOR
"Let's take a little off the top ... a bit off the sides ...
trim the back a bit ... Surprise ! You've been bald-ed !"