scott@electron.amd.com (Scott McMahon) (05/10/91)
In article <3401@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes: | | [discussion of vector vs superscalar and smart cache interaction | removed..] | | A "preload cache" instruction or bit to change the cache state to the | above behavior are other possibilities. Preloading the cache may also be done by adding to the framework of the architecture without adding a new instruction. In the case of the *new* Am29030, the special-purpose register interface is used to access the instruction cache directly for reading and writing (ie. preloading or testing). Two new special-purpose registers were added to provide a data path (Cache Data Register - CDR) and a control path (Cache Interface Register - CIR) to the cache. Both the cache instruction rams and the cache tag rams may be accessed through this mechanism. Protection and such are handled by the existing mechanisms for special-purpose register protection. -Scott -- Scott McMahon - 29k Advanced Processor Development - Advanced Micro Devices scott@amd.com (800) 531-5202 x54985