tak@lfcs.ed.ac.uk (Tom Kean) (07/01/88)
Assuming you had a massive array of very small flexible cells
programmed by writing into RAM, each
cell capable of implementing any 2 input, 1 output logic gate or a latch
and allowing full connectivity between neighbouring cells plus a limited
number of global connections what sort of algorithms could you implement?
I am looking for some example applications for my PhD thesis
illustrating potential uses for very large
arrays of flexible cells: two obvious ones are extremely fast DES
encryption and gate-level simulation of ASIC designs. Are there any
others: preferably in an area where conventional computers and array
processors fail miserably? Three general criteria would be
1. Mainly local communication.
2. Potentially massive parallelism.
3. Basic repeating units simple enough to design at the gate level.
I should make it clear that a 1 million gate EPLD is not complete
science fiction it would be composed of 256, 4096 (=64x64) cell array
chips - implemented in 1um CMOS technology each chip would require just
over 1cm^2.
Please reply to me and I will summarize responses if there is enough
interest. I would also be interested in out of the way applications
for small or medium sized arrays.
Tom Kean.