napi@rangkom.MY (Mohd Hanafiah b. Abdullah) (10/13/89)
I may have missed the obvious, but how would one implement semaphore type operations on a MIPS machine as I have not noticed any "test and set" instruction available. External hardware perhaps? Thanks in advance. Mohd Hanafiah Abdullah GO BIG RED !!! I.U. 1987 NCAA Basketball Champions.
mark@mips.COM (Mark G. Johnson) (10/14/89)
In article <200@rangkom.MY> napi@rangkom.MY (Mohd Hanafiah b. Abdullah) writes: >I may have missed the obvious, but how would one implement >semaphore type operations on a MIPS machine as I have not >noticed any "test and set" instruction available. External hardware >perhaps? > $ From: jeffd@norge.sgi.com (Jeff Doughty) $ Newsgroups: comp.sys.mips $ Subject: Re: atomic instructions on R2000 $ Message-ID: <769@odin.SGI.COM> $ Date: 3 Oct 89 15:24:39 GMT $ > This may be a naive question, but... $ $ > In Kane's MIPS R2000 book, I can't find any reference to $ > atomic instructions, like swap or test-and-set. Are there $ > really none, or am I missing something? If not, how do $ > MIPS-based multiprocessors implement locks? $ $ $ It is not naive at all. The SGI PowerSeries machines, which use $ multiple R2000's and R3000's implement test-and-set spinlocks with $ a custom gate-array per processor and a private bus. The gate-array $ is actually a bus-watching cache that maintains the state of 64K $ spinlocks. We kernel guys grab 32K and allow the users 32K. They $ are mapped into a process's address space and accessed like memory. $ $ Moving the synchronization traffic to a separate bus has several $ advantages - the primary reason being that it takes load off the $ memory bus. In addition, we can taylor the latency requirements $ and cache coherency protocols to lock traffic, rather than having $ one bus design that does everything non-optimally). $ $ Jeff Doughty $ IRIX group $ Silicon Graphics, Inc. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 (408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}
jas@postgres.uucp (James Shankland) (10/15/89)
In article <29463@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >In article <200@rangkom.MY> napi@rangkom.MY (Mohd Hanafiah b. Abdullah) writes: >>[How do you do atomic test and set on MIPS?] > $ From: jeffd@norge.sgi.com (Jeff Doughty) > $ Subject: Re: atomic instructions on R2000 > $ Date: 3 Oct 89 15:24:39 GMT > > ... > $ [By using a private bus and external gate-array per processor.] > $ The gate-array is actually a bus-watching cache that maintains the > $ state of 64K spinlocks.... That's pretty interesting. But there's another aspect to the original question: how do you do atomic test-and-set on a uniprocessor MIPS system, without atomicity being broken by preemption? In kernel mode, presumably you can always disable interrupts, do the test, do the set, and re-enable interrupts. But what about in user mode? It's awfully handy if user processes sharing memory can do atomic t&s without a kernel call .... jas
hjm@cernvax.UUCP (Hubert Matthews) (10/15/89)
In article <200@rangkom.MY> napi@rangkom.MY (Mohd Hanafiah b. Abdullah) writes: > >I may have missed the obvious, but how would one implement >semaphore type operations on a MIPS machine as I have not >noticed any "test and set" instruction available. External >hardware perhaps? Do it in software using Leslie Lamport's Fast Mutual Exclusion Algorithm, ACM TOCS vol 5, no 1, Feb 87, pp 1-11. -- Hubert Matthews ...helping make the world a quote-free zone... hjm@cernvax.cern.ch hjm@vxomeg.decnet.cern.ch ...!mcvax!cernvax!hjm
rogerk@mips.COM (Roger B.A. Klorese) (10/17/89)
In article <18381@pasteur.Berkeley.EDU> jas@postgres.berkeley.edu (Jim Shankland) writes: >How do you do atomic test-and-set on a uniprocessor MIPS >system, without atomicity being broken by preemption? In kernel mode, >presumably you can always disable interrupts, do the test, do the set, >and re-enable interrupts. But what about in user mode? It's awfully >handy if user processes sharing memory can do atomic t&s without a >kernel call .... In our current release, you don't (despite the following entry in our documentation, which was entered too early). But in our forthcoming release, you would use the sysmips(MIPS_ATOMIC_SET,...) system call: SYSMIPS(2-SysV) RISC/os Reference Manual SYSMIPS(2-SysV) When cmd is MIPS_ATOMIC_SET, two arguments are expected. The first argument should be the address of an int variable, and the second argument should be an int value. This com- mand atomically sets the variable to the value supplied and returns the old value of the variable. Note that if the old value of the variable may be -1, it is not possible to dis- tinguish that return from an error return, except by setting the errno variable to 0 before calling sysmips() and testing whether errno is non-zero on return. -- ROGER B.A. KLORESE MIPS Computer Systems, Inc. phone: +1 408 720-2939 928 E. Arques Ave. Sunnyvale, CA 94086 rogerk@mips.COM {ames,decwrl,pyramid}!mips!rogerk "I want to live where it's always Saturday." -- Guadalcanal Diary