lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (03/25/89)
What follows is the publicly revealed information about Data General's
upcoming ECL M88000. I'm posting it in the hopes of stirring up a good
fight, particularly as concerns the cache organization. Perhaps the
nice people doing the ECL MIPS, the GaAs MIPSes, the ECL SPARC, and the
GaAs SPARC, would like equal time.
Technology:
Motorola ECL gate arrays, 50,000 gates each.
Stated as 40 watts per chip, but surely they meant per-chip-set.
Air cooled.
CPU:
One ECL chip for integer, one for float. Two copies of the registers.
140 MHz ( ~7 ns clock ).
Pipeline can overlap Integer/FADD/FMUL execution.
DFADD takes 4 clocks, no pipelining within FADD unit.
SFMUL takes 6 clocks, no pipelining within FMUL unit.
DFMUL takes 8 clocks, no pipelining within FMUL unit.
Cache/MMU:
One ECL chip plus static RAM chips.
Four caches, not two.
First level I & D caches have 5 ns access chips ( 2Kx1 is mentioned )
Second level I & D caches have 12 ns access chips ( 8Kx1 is mentioned )
First level can be 8KB-256KB, 16KB is mentioned.
Second level can be 64KB-1MB, 128KB is mentioned.
Not clear if those sizes are for I & D together or separately.
Cache timing:
If first level hits, it can supply 1 op word + 1 data word per clock.
Store bandwidth is one data word per two clocks.
Third op after a load op, can use the loaded data without causing a stall.
A first-level read miss, that hits in the second level,
costs two or three extra clocks, I'm not sure which.
Cache organization:
All caches are direct mapped.
First level uses virtual addresses, second level uses physical.
First level always writes through to the second.
Second level's write policy is software selectable.
Second level can translate physical addresses to virtual,
presumably on behalf of the bus snooper.
It insures that the first level never has multiple
entries for one physical address.
--
Don D.C.Lindsay Carnegie Mellon School of Computer Science
-- bcase@cup.portal.com (Brian bcase Case) (03/26/89)
>upcoming ECL M88000. >Technology: > Motorola ECL gate arrays, 50,000 gates each. > Stated as 40 watts per chip, but surely they meant per-chip-set. > Air cooled. Sorry, they actually do mean 40 WATTS PER CHIP!!!!!
rick@pcrat.UUCP (Rick Richardson) (03/26/89)
In article <16232@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes: >>upcoming ECL M88000. >> Motorola ECL gate arrays, 50,000 gates each. >> Stated as 40 watts per chip, but surely they meant per-chip-set. >> Air cooled. >Sorry, they actually do mean 40 WATTS PER CHIP!!!!! In that case, it sounds to me like they must use Zip Cord to get the juice to the chip, and air cooling, as long as you are in Fairbanks. Isn't the current requirement something like 40/5.2 ~= 7.5 amps? -- Rick Richardson | JetRoff "di"-troff to LaserJet Postprocessor|uunet!pcrat!dry2 PC Research,Inc.| Mail: uunet!pcrat!jetroff; For anon uucp do:|for Dhrystone 2 uunet!pcrat!rick| uucp jetroff!~jetuucp/file_list ~nuucp/. |submission forms. jetroff Wk2200-0300,Sa,Su ACU {2400,PEP} 12013898963 "" \d\r\d ogin: jetuucp
les@unicads.UUCP (Les Milash) (03/28/89)
regarding: Sorry, they actually do mean 40 WATTS PER CHIP!!!!! yeah, Moto's the first to figure out how to hang 133 little pins out the bottom of a TO-5 package. T--T Les Milash (w)303-443-6961 graphix s/w slave, Unicad Inc. /| /| (h)303-444-8552348 Arapahoe #17 Boulder CO USA 80302 T-+T | my opinions are so different from those of my employer :-( | T+-T that i often look for a different employer :-) |/ |/ and that's what these are. T--T
keith@mips.COM (Keith Garrett) (03/30/89)
In article <4559@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: [blurb on Data General's 88k ecl implementation] > One ECL chip for integer, one for float. Two copies of the registers. gee, doesn't the 88k have a single register file. must be hell maintaining register coherency. -- Keith Garrett "This is *MY* opinion, OBVIOUSLY" UUCP: keith@mips.com or {ames,decwrl,prls}!mips!keith USPS: Mips Computer Systems,930 Arques Ave,Sunnyvale,Ca. 94086