kruger@whyvax.dec.com (Bear with me) (03/10/88)
So your hardware gets clobbered by certain patterns of access. ok.... Consider 4 separate banks of memory, each interleaved <n> times (up to you). Each one has some cache, and an intelligent controller that will load the cache upon command, with (possibly a range?) of memory. Now, even for situations where the pattern of access is completely irregular, but static (such as when dealing with a bunch of variables, for instance) you can pre-load those variables into the cache, and have them ready before the processor needs them. Important areas where requirements can be predicted in advance include: a) many array-references b) almost all scalar expressions c) code Code itself is an interesting case. By "pre-caching" you have saved time on the first load in some cases. This is probably not worth it in a general purposemachine, but on a supercomputer where you are going for broke, it might be. Note that I am not talking about loading the *next* instruction, but rather the next <n>. You dedicate a bank to code, and if you can load enough into cache, can almost always hit even on branch forwards.... The compiler aspects are interesting. You have to keep track of different banks,different interleave within a bank, and commanding pre-loading at the proper time. But I believe a system could be made to exploit this concept. dov