uuuj@vax1.UUCP (Rodney Recker) (02/26/88)
I've now seen several references to Harvard Architecture and am wondering what it really is that qualifies an architecture as "Harvard". Any explainations or references would be appreciated. Thanks in advance! Rod Recker
tedc@eleazar.Dartmouth.EDU (Ted Cooley) (03/01/88)
The Harvard Class of computer architecture is characterized by separate data and instruction memories. This is in contrast to the Princeton or Van Neumann (sp) Class with only one memory for data and instructions. ...tedc@eleazar.dartmouth.edu Edmond S. Cooley Thayer School of Engineering Dartmouth College
oconnor@sungoddess.steinmetz (Dennis M. O'Connor) (03/02/88)
An article by uuuj@vax1.UUCP (Rodney Recker) says:
] I've now seen several references to Harvard Architecture and am
] wondering what it really is that qualifies an architecture as
] "Harvard". Any explainations or references would be appreciated.
]
] Thanks in advance!
]
] Rod Recker
"HARVARD" architectures have seperate memory systems for instructions
and operands. Separate busses connect each memory system to the CPU.
The name is historical, I believe : one of the very early machines
that had this architecture was built at Harvard.
The idea is old, but has aquired popularity recently as
a method to method the CPU/Memory bandwidth bottleneck
in microcomputers.
A varient of it is to hae separate instruction and data
busses to seperate instruction and data memories, but
with a shared address bus.
Most Harvard architectures need to "dual-port" the
instruction memory onto the operand memory. Often
Time-Division Multiplexing is used, at a rather course scale,
essentially by placing a DMA channel between the I and D memories,
rather than true dual-port memory or fine-grain TDM.
--
Dennis O'Connor UUNET!steinmetz!sunset!oconnor
ARPA: OCONNORDM@ge-crd.arpa
(-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)