mark@mips.COM (Mark G. Johnson) (01/16/90)
In article <105@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes: > >But doesn't CMOS get just as hot when you start clocking it at ECL speeds. >Or if not as hot, close enough to have serious power and cooling problems. > According to Intel, No. And this isn't just religious dogma, they have something that comp.arch all too often does not: measured data. At their ISSCC presentation on the i860 (a CMOS microprocessor having onboard CPU, floating point, and cache memory) they said that some parts would run at 50 MHz and, at that clock rate, dissipate only 2.5 Watts*. This is considerably less power than either the B5000 (ECL SPARC) or the R6000 (ECL MIPS) burn at 80 MHz. For a fair comparison you'd have to further cut the CMOS power by a factor of three, since the i860 includes F.P. and cache whereas the B5000 and R6000 are CPUs only. Other data to take notice of: CMOS uP's will soon operate from 3.3 volts ** which will reduce power dissipation by a factor of 2.3 [ = (5/3.3)^2 ]. It's doubtful that merchant ECL will reduce VEE as quickly, because that would mean giving up 3-level series gated logic, which is an extremely useful and often-exploited feature of present ECL. The ECL camp isn't sitting still, of course. IBM and Unisys have been using a variant called CML for years, which operates off 3.0 volts and works just fine without series gating. However the _power_ benefits for ECL/CML scale as a linear function of voltage whereas in CMOS it's a squarelaw function. Another development is pin-for-pin, drop-in replacements foc VLSI ECL gate arrays made in Gallium Arsenide. Convex is using these pretty extensively. Vendors claim GaAs will go the same speed as ECL but burn 1/4 the power. Opinion, not data, follows; flame-broil me if you must... On each project, chip engineers design their parts to fit within the power budget allocated for that chip. That's why you can't take the power per transistor per megahertz of the 386, multiply it by the number of transistors on the i860 times the clock rate of the i860, and get the power dissipation of the i860. The 386 and the 860 were each _designed_ for a particular power dissipation. Apparently the 860's goal was moderately low power; hat's off to R. Albers &co for getting it so low. -------------------------------------------------------------------------- * Of course these are measured data on a few units and Intel has to write the datasheet spec more conservatively, with the Gaussian distribution in mind. ** Note that 3/4 of the requirements for 3.3 volt operation were available in 1989: 3.3 volt ASICs, 3.3 volt memories, and 3.3 volt glue logic. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 (408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}
slackey@bbn.com (Stan Lackey) (01/17/90)
In article <34525@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >In article <105@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes: > >But doesn't CMOS get just as hot when you start clocking it at ECL speeds. > >Or if not as hot, close enough to have serious power and cooling problems. >According to Intel, No. And this isn't just religious dogma, they have >something that comp.arch all too often does not: measured data. At their >ISSCC presentation on the i860 (a CMOS microprocessor having onboard CPU, >floating point, and cache memory) they said that some parts would run at >50 MHz and, at that clock rate, dissipate only 2.5 Watts*. This is I wonder if the conditions under which they quote power are the same as those under which they quote performance: all pipes full, dual instruction mode, mul-accum instructions, graphics operations running? I mean, dissipation is proportional to load capacitance, which is going to be proportional to the number of nodes switching (ref: "halt and catch fire" instruction). Also, can it be that the faster chips in a lot are faster due to lower capacitance? PS the story I heard was Convex is using TTL-compatible GaAs PALs, not ECL. :-) Stan
ecsv12@castle.ed.ac.uk (T Stiemerling) (01/17/90)
CMOS gates (inverters etc.) when constructed in regular `complementary' fashion do not dissipate much heat since current only flows when there is a change in the input, ie dynamic power dissipation only, whereas NMOS for example dissipates power statically (one of the advantages of CMOS). CMOS is constructed using FET's while ECL is constructed from bipolar transistors, which probably also dissipate heat statically (although I'm not sure), leading to the greater heat dissipation and power consumption of ECL devices over CMOS devices being clocked at the same speed. -- Tom Stiemerling, Computer Science Department, Edinburgh University, Edinburgh, UK. : 031-667 1081 : T.R.Stiemerling@uk.ac.edinburgh
toms@omews44.intel.com (Tom Shott) (01/18/90)
In article <34525@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
Opinion, not data, follows; flame-broil me if you must...
On each project, chip engineers design their parts to fit within the
power budget allocated for that chip. That's why you can't take the
power per transistor per megahertz of the 386, multiply it by the
number of transistors on the i860 times the clock rate of the i860,
and get the power dissipation of the i860. The 386 and the 860 were
each _designed_ for a particular power dissipation. Apparently the
860's goal was moderately low power; hat's off to R. Albers &co for
getting it so low.
Both higher performance and level power dissipation for new processors are a
result of improved fabrication processes. Improved processes have smaller
feature sizes which result in 1M + transistor chips. It also means more
devices for the same Cap value. Thus higher performance with a flat power
curve.
Opinion On:
I don't speak for Intel. (Well, hardly ever). Data sheets often have a
maximum power dissipation. This number is arrived at by finding a group of
chips at the edge of passing specs. Then all the available test sets are
run on the chips at the conditions stated in the specs for DC values and
loads. The highest power consumption noted is used. Thus your mileage may
very depending on output loading, software, etc. I don't know how we arrive
at "typical" power dissipation.
Opinion Off:
--
-----------------------------------------------------------------------------
Tom Shott INTeL, 2111 NE 25th Ave., Hillsboro, OR 97123, (503) 696-4520
toms@omews44.intel.com OR toms%omews44.intel.com@csnet.relay.com
INTeL.. Designers of the 960 Superscalar uP and other uP'sgillies@p.cs.uiuc.edu (01/18/90)
This is very interesting. Perhaps someone should write a "meltdown"
benchmark to test CMOS microprocessors. The program counter should
continually oscillate between two complementary binary numbers. All
registers should be complemented as often as possible. On the i860,
all 3 dispatched instructions should cause complementation on every
cycle. If you knew the internal architecture, I'm sure you could
torture other registers too. Maybe block-load all the registers with
-1 and then execute an instruction to zero all registers at once. I
wonder how much of a power transient is possible on a CMOS
microprocessor.....
Don Gillies, Dept. of Computer Science, University of Illinois
1304 W. Springfield, Urbana, Ill 61801
ARPA: gillies@cs.uiuc.edu UUCP: {uunet,harvard}!uiucdcs!gillieskyriazis@herodotus.rdrc.rpi.edu (George Kyriazis) (01/19/90)
In article <1662@castle.ed.ac.uk> ecsv12@castle.ed.ac.uk (T Stiemerling) writes: >CMOS is constructed using FET's while ECL is constructed from >bipolar transistors, which probably also dissipate heat statically ECL's are using a differential amp at the input with a constant current source (I don't remember the rating). They are dissipating the same massive amount of current anyway. Those guys work on current, not voltage, that's why they are power hogs. >-- >Tom Stiemerling, Computer Science Department, Edinburgh University, >Edinburgh, UK. : 031-667 1081 : T.R.Stiemerling@uk.ac.edinburgh George Kyriazis kyriazis@turing.cs.rpi.edu kyriazis@rdrc.rpi.edu ------------------------------