lindsay@k.gp.cs.cmu.edu (Donald Lindsay) (06/21/88)
There hasn't been any discussion of the new package that Motorola announced for its "Hypermodule". Basically, they are moving from pin-grid packages with 100-mil centers, to pad-grids with 60-mil centers. This cleans up the board layout, since buried layers don't have to make room for all those big fat pins. It also increases the connections per square inch from 100 to 277, i.e. almost triple the density. Specifically, it allows the 88100 CPU to have four 32-bit paths and still be in a package 1.1" on a side. This is Neat, of course, because density equates to progress. (I remember the backpanel of the PDP-5: it looked like you soldered the pins with a 50 watt iron. I tried to look inside an LGP-30 (drum machine) once, but the wire mat was too many inches thick to see through.) I have a few questions. For one, why did Motorola feel the need to use 102 pads (YES - ONE HUNDRED AND TWO PADS) just to conduct heat? (And what do TAB packagers do with heat?) I suppose that this package will allow higher clock rates than pin grid arrays do. Do we have any experts on the net, who can comment on how soon that will actually matter? Also, it used to be that package designers were very worried about allowing visual inspection of joints (IBM notwithstanding). Did this worry just go away? Can these things be socketed? -- Don lindsay@k.gp.cs.cmu.edu CMU Computer Science "Imitation is not the sincerest form of flattery. Payments are." - a British artist who died penniless before copyright law.
stevew@nsc.nsc.com (Steve Wilson) (06/22/88)
In article <2016@pt.cs.cmu.edu> lindsay@k.gp.cs.cmu.edu (Donald Lindsay) writes: > >There hasn't been any discussion of the new package that Motorola announced >for its "Hypermodule". > >Basically, they are moving from pin-grid packages with 100-mil centers, to >pad-grids with 60-mil centers. This cleans up the board layout, since >buried layers don't have to make room for all those big fat pins. It also >increases the connections per square inch from 100 to 277, i.e. almost >triple the density. Specifically, it allows the 88100 CPU to have four >32-bit paths and still be in a package 1.1" on a side. > I just wonder how many board layout packages are broken by this new packaging scheme? I know alot of them are hard-wired to only be capable of working on 100 mil or 50 mil grid! Steve Wilson National Semiconductor [This is my opinion only, not that of my employer's]
mslater@cup.portal.com (06/23/88)
> pad array carriers for 88000
Motorola is indeed using these new packages for building their "HYPERmodules",
which are ceramic substrates with 1-4 cpus and 2-8 cpmmus on them.
The problem with this package is that it must be surface mounted, and
visual inspection is not possible. I don't think there is any socket for it.
Thus, Moto isn't selling bare chips in this package -- most users don't have
the capability to use it.
BTW, I've been told that this packaging technology was developed by Moto's
cellular telephone group, which will build the HYPERmodules for the computer
division.
Michael Slater, Microprocessor Report sun!portal!cup.portal.com!mslater