tada@athena.mit.edu (Michael Zehr) (11/06/88)
In article <10722@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes: >The architecture has little if anything to do with this. The compiler >is a comparatively-meager one-time investment, and getting a good one >is very important. A good optimizing compiler is probably easier to >write for a simple machine (e.g. RISC) than for a complex machine. A "simple" machine? To use RISC to it's full benefit you have to try and cut CPU to memory data exchange, keep piplines well-filled, probably try to keep memory references in burst to increase cache hit rate. My guess is that's it's easier to write a working compiler for RISC than for CISC, but a good optimizing compiler would have to be very complicated. DISCLAIMER: I don't write compilers. I mostly just use them. But I've read a number of articles saying that the main advantage of RISC is only reached when you have a complicated compiler that uses all the fancy hardware in the machine. Any comment by people who have written compilers for both RISC anc CICS??? -michael j zehr
henry@utzoo.uucp (Henry Spencer) (11/08/88)
In article <7832@bloom-beacon.MIT.EDU> tada@athena.mit.edu (Michael Zehr) writes: >A "simple" machine? To use RISC to it's full benefit you have to try and >cut CPU to memory data exchange, keep piplines well-filled, probably try >to keep memory references in burst to increase cache hit rate. Precisely the same is true of CISCs, and the much greater complexity of the machine makes it harder to predict the effects of these factors. Do *you* know how to keep pipelines well-filled or cache hit rate up on a VAX 8600? Does anybody? I sure don't. On a 29000 or a MIPS chip, it's not that hard to figure out. -- The Earth is our mother. | Henry Spencer at U of Toronto Zoology Our nine months are up. |uunet!attcan!utzoo!henry henry@zoo.toronto.edu
bcase@cup.portal.com (Brian bcase Case) (11/08/88)
>A "simple" machine? To use RISC to it's full benefit you have to try and >cut CPU to memory data exchange, keep piplines well-filled, probably try >to keep memory references in burst to increase cache hit rate. These things must also be done to use CISC to its full benefit. Don't take my word for it, ask anyone who has written a compiler for a high- performance processor. The bottom line is that these things are more *beneficial* on a simple processor like a RISC. (I don't understand why you quoted simple.) >My guess is that's it's easier to write a working compiler for RISC than >for CISC, but a good optimizing compiler would have to be very complicated. >DISCLAIMER: I don't write compilers. I mostly just use them. But I've read >a number of articles saying that the main advantage of RISC is only reached >when you have a complicated compiler that uses all the fancy hardware in the >machine. Who wrote those articles? Would you buy a used PDP-8 from them? >Any comment by people who have written compilers for both RISC anc CICS??? Oh, call on me! call on me! From one who has done more than guess about the relative ease (I'm not flaming, just pointing out that I speak from some experience) of writing compilers, designing architectures, and implementing processors, I can tell you that optimization algorithms, at least the machine-independent ones, are pretty much the same for all architectures. The *fact* of the matter is that RISCs make determining when the optimizations are beneficial straightforward. CISCs make determining when the optimizations are beneficial a NIGHTMARE. Choosing addressing modes, deciding on register allocation, etc. all depend on each other in a CISC; this leads to a combinatorial explosion of possibilities, one that cannot be dealt with except to limit the search space, i.e., to subset the architecture. This must be tiring to everyone here. The main advantage of all architectures is reached only when you have a great compiler that uses all the fancy everything in machine. RISC makes writing that compiler eaiser. If you don't believe that, there's little I can do here to convince you otherwise.