[comp.arch] Instruction Frequency

lindsay@gandalf.cs.cmu.edu (Donald Lindsay) (12/09/90)

>>In article <9012070105.AA02416@hcrlgw.crl.hitachi.co.jp>,
>>	joe@hcrlgw.crl.hitachi.co.JP (Dwight Joe) writes:
>>
>>                  instruction       dynamic frequency
>>                     I[1]                22%
>>                     I[2]                8%

One of the difficulties with this sort of analysis is that different
classes of programs give different results. Worse; different
compilers emit different styles of code. This can come from:
	data types (Cobol strings),
	addressing model (APL expression stack),
	calling convention (Modula-2 uplevel addressing),
	execution model (Icon control backtracking),
	mode (debug, profiling),
	OS environment (Mach threads calling reentrant library routines),
	system environment (the different FPUs that Sun has sold),
	application (linpack != TCP/IP),
	the age of the compiler (i860 pipeline mode),
etc.

Marty Hopkins of IBM expressed an interesting philosophy here: he
said that they looked at the data flows, and didn't care if they
added a lot of instructions to support those flows. (I take that
statement with a certain amount of salt, since the result was still a
load/store machine with simple instruction encoding. He was to some
extent referring to superscalar data flows.)

Would anyone like to educate me on the different code styles found
on the latest RISC machines? MIPS has a COBOL, no?
-- 
Don		D.C.Lindsay .. temporarily at Carnegie Mellon