[comp.arch] Cerberus multiprocessor simulator

brooks@lll-crg.llnl.gov (Eugene D. Brooks III) (02/02/88)

Anyone interested in a simulator for a scalable shared memory multiprocessor
architecture with k^n fully pipelined processors connected to k^n memory
modules through a packet switched network ought to fire me off a mail.

The simulator is available as a BINARY release and can be accessed via
ftp from the internet.  Configurations for the Sequent Balance, Alliant FX
and SUN 3 are available at the moment.  A version for the Sequent Symmetry
can be built upon request.  On a multiprocessor, the multiprocessor simulator
itself is a shared memory parallel program, and is written in the very same
programming model used to write code for the simulator.  We will entertain
only a binary release at the moment, if you do not have one of the machines
listed above let us know and we will see if we can do something for you.

A complete set of compiler/optimizer/assembler/loader tools for a parallel
extension of C programming language is part of the package.

Forward me an email if you are interested and I will tell you how to access
the package and add your name to the Cerberus mailing list.  The current
release is a BETA release of the package, but we have been using the system
locally for more than a year.  All documentation is contained in the release
in postscript format, but we can mail copies of the documents via the SNAIL
if need be.