daveb@geaclib.UUCP (David Collier-Brown) (10/30/88)
| In article <10778@reed.UUCP>, mdr@reed.UUCP (Mike Rutenberg) writes: [...] | Does the system have multiported memory so that the 370 can get at | it from one end while the channel controllers get at it from the | other? Sure does! On a 'bun (Honeywell DPS-8, the basic GCOS/Multics machine) the memory is the middle of a circle of devices, much like a wagon train surrounded by indians. The connections are through so-called "system controllers", which provide multi-port-like access to memory, devices and cpu's, and prevent literally simultaneous access. The i/o processors sit outside this ring and hurl large masses of data to and from disk, tape and front-end processors. The cpu's also sit here, and modify the contents of the main memory, typically by reading and writing strips (say, 8 words or 8 * 4 * 9 = 288 bits). The i/o processors are somewhat special-purpose, the disk and tape controllers less so and the front-end processors are normal general purpose machines, sold as stand-alones as the DPS-6 line. The cpu's are vCISC, with simple register operations, complex memory-to-memory operations and now moderately complex vector-to-vector memory operations. (You can see how the wide fetch makes vectorization an obvious good idea). The cpu's get a reasonable degree of speed by the fetch granularity and by fairly long pipelines, with the pipelines triplicated in the larger models to allow one to decode "both sides" of a branch. The system controllers are definitely special-purpose, and quite fast. They're also magic... I know almost nothing about them. They presumably have some close relationship with the Multics memory manager hardware, and the similar domain-managment hardware on late models of GCOS. One thing I do know is that the whole idea of a "bus mini" tends to make the (Honeywell-Bull) mainframers laugh. They expect that as the newer, smaller machines become faster, that they will have to make memory and memory bandwidth the center of their system and their efforts... The 'bun people have gone about as far as they can with pipelining and simple cache schemes and still find that main memory contention is the "limiting variable". --dave c-b Disclaimer: The above opinions are about three years out-of-date, and may contain inadvertent errors due to MY memory access problems. -- David Collier-Brown. | yunexus!lethe!dave Interleaf Canada Inc. | 1550 Enterprise Rd. | HE's so smart he's dumb. Mississauga, Ontario | --Joyce C-B