eugene@wilbur.nas.nasa.gov (Eugene N. Miya) (07/03/90)
Mail corrections, additional editorial commentary (most important,
only, REAL architects do this), to me. I only plan to add the refs
relevant to parallelism to my bibliography. State if you want anonmyous
or attributed annotation (%X) fields. I have not attributed the quotes
given me so far. If you want "abstracts," you type them in.
P.S. these were scanned in.
--e. nobuo miya, NASA Ames Research Center, eugene@orville.nas.nasa.gov
{uunet,mailrus,other gateways}!ames!eugene
%h $Revision$ $Date$
%A Sarita V. Adve
%A Mark D. Hill
%T Weak Ordering-A New Definition
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 2-14
%K shared-memory multiprocessor, sequential consistency, weak ordering,
%K Multiprocessor Synchronization and Sequential Consistency
%A Kourosh Gharachorloo
%A Daneil Lenoski
%A James Laudon
%A Philip Gibbons
%A Anoop Gupta
%A John Hennessy
%T Memory Consistency and Event Ordering in Scalable Shared-Memory
Multiprocessors
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 15-26
%K Multiprocessor Synchronization and Sequential Consistency
%A Joonwon Lee
%A Umakishore Ramachandran
%T Synchronization with Multiprocessor Caches
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 27-37
%K Multiprocessor Synchronization and Sequential Consistency
%A Po-Jen Chuang
%A Nian-Feng Tzeng
%T Dynamic Processor Allocation in Hypercube Computers
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 40-49
%K Multiprocessor Network Issues
%A Abdou Youssef
%A Bruce Arden
%T A New Approach to Fast Control of $r sup 2 times r sup 2$
3-Stage Benes Networks of $r times r $Crossbar Switches
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 50-59
%K Multiprocessor Network Issues
%A William J. Dally
%Z MIT
%T Virtual-Channel Flow Control
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 60-68
%K Multiprocessor Network Issues
%A Shekhar Borkar
%A Robert Cohn
%A George Cox
%A Thomas Gross
%A H. T. Kung
%A Monica Lam
%A Margie Levine
%A Brian Moore
%A Wire Moore
%A Craig Peterson
%A Jim Susman
%A Jim Sutton
%A John Urbans
%A Jon Webb
%T Supporting Systolic and Memory Communication in iWarp
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 70-81
%K Special-Purpose Architectures
%A Gregory M. Papadopoulos
%A David E. Culler
%T Monsoon: An Explicit Token-Store Architecture
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 82-91
%K Special-Purpose Architectures
%A Marco Annaratone
%A Marco Fillo
%A Kiyoshi Nakabayashi
%A Marc Viredaz
%T The K2 Parallel Processor: Architecture and Hardware Implementation
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 92-101
%K Special-Purpose Architectures
%A Anant Agarwal
%A Beng-Hong Lim
%A David Kranz
%A John Kubiatowicz
%T APRIL: A Processor Architecture for Multiprocessing
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 104-114
%K Shared-Memory Multiprocessors
%A Roberto Bisiani
%A Mosur Ravishankar
%T PLUS: A Distributed Shared-Memory System
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 115-124
%K Shared-Memory Multiprocessors
%A John K. Bennett
%A John B. Carter
%A Willy Zwaenepoel
%T Adaptive Software Cache Management for
Distributed Shared Memory Architectures
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 125-134
%K Shared-Memory Multiprocessors
%A David R. Ditzel
%A John L. Hennessy
%A Bernie Rudin
%A Alan J. Smith
%A Stephen L. Squires
%A Zeke Zalcstein
%A Mark D. Hill
%T Big Science Versus Little Science -- Do You Have to Build It?
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 136
%K Panel Session
%A Brian W. O'Krafka
%A A. Richard Newton
%T An Empirical Evaluation of Two Memory-Efficient Directory Methods
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 138-147
%K Cache Memory
%A Daniel Lenoski
%A James Laudon
%A Kourosh Gharachorloo
%A Anoop Gupta
%A John Hennesy
%T The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 148-159
%K Cache Memory
%A Steven Przybylski
%T The Performance Impact of Block Sizes and Fetch Strategies
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 160-169
%K Cache Memory
%A D. Alpert
%A A. Averbuch
%A O. Danieli
%T Performance Comparison of Load/Store and
Symmetric Instruction Set Architectures
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 172-181
%K Instruction Sets
%A Jack W. Davidson
%A David B. Whalley
%T Reducing the Cost of Branches by Using Registers
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 182-191
%K Instruction Sets
%A Carl E. Love
%A Harry F. Jordan
%T An Investigation of Static Versus Dynamic Scheduling
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 192-201
%K Instruction Sets
%X This paper took a lot of "heat."
%A Dileep Bhandarkar
%A Richard Brunner
%T VAX Vector Architecture
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 204-215
%K Processor Implementations, VAX 9000, VAX 6000, Trilogy,
%X Architecture compromised vector architecture for multiple processors.
More closely patterned after Cray-1 rather than X-MP (1 data path to
memory rather than 3 or 5). Interesting module packaging.
%A Robert W. Horst
%A Richard L. Harris
%A Robert L. Jardine
%T Multiple Instruction Issue in the NonStop Cyclone Processor
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 216-226
%K Processor Implementations
%X NonStop and Cyclone are trademarks of Tandem Computer.
%A Shreekant S. Thakkar
%A Mark Sweiger
%T Performance of an OLTP Application on Symmetry Multiprocessor System
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 228-238
%K Applications
%A Ding-Kai Chen
%A Hong-Men Su
%A Pen-Chung Yew
%T The Impact of Synchronization and Granularity of Parallel Systems
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 239-248
%K Applications
%A Hakon O. Bugge
%A Ernst H. Kristiansen
%A Bjorn O. Bakka
%T Trace-Driven Simulations for a Two-Level Cache Design in Open Bus Systems
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 250-259
%K Memory Traces and Simulation
%A Jiun-Ming Hsu
%A Prithviraj Banerjee
%T Performance Measurement and Trace Driven Simulation of Parallel CAD
and Numeric Applications on a Hypercube Multicomputer
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 260-269
%K Memory Traces and Simulation
%A Anita Borg
%A R. E. Kessler
%A David W. Wall
%T Generation and Analysis of Very Long Address Traces
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 270-279
%K Memory Traces and Simulation
%A Bruce K. Holmer
%A Barton Sano
%A Michael Carlton
%A Peter Van\ Roy
%A Ralph Haygood
%A William R. Bush
%A Alvin M. Despain
%A Joan M. Pendleton
%A Tep Dobry
%T Fast Prolog with an Extended General Purpose Architecture
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 282-291
%K Prolog/Potpourri
%A Leon Alkalaj
%A Tomas Lang
%A Milos Ercegovac
%T Architectural Support for the Management of Tightly-Coupled Fine-Grain
Goals in Flat Concurrent Prolog
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 292-301
%K Prolog/Potpourri
%A Samuel Ho
%A Lawrence Snyder
%T Balance in Architectural Design
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 302-310
%K Prolog/Potpourri
%A A. L. Narasimha Reddy
%A Prithviraj Banerjee
%T A Study of I/O Behavior of Perfect Benchmarks on a Multiprocessor
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 312-321
%K I/O, input/output,
%A Peter M. Chen
%A David A. Patterson
%T Maximizing Performance in a Striped Disk Array
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 322-331
%K I/O, input/output,
%A Kang G. Shin
%A Greg Dykema
%T A Distributed I/O Architecture for HARTS
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 332-342
%K I/O, input/output,
%A Michael D. Smith
%A Monica S. Lam
%A Mark A. Horowitz
%Z Stanford
%T Boosting Beyond Static Scheduling in a Superscalar Processor
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 344-354
%K High-End Design
%A George Taylor
%A Peter Davies
%A Michael Farmwald
%Z MIPS
%T The TLB Slice--A Low-Cost High-Speed Address Translation Mechanism
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 355-363
%K High-End Design
%A Norman P. Jouppi
%Z DEC
%T Improving Direct-Mapped Cache Performance by the Addition of
a Small Fully-Associative Cache and Prefetch Buffers
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 364-373
%K High-End Design
%A Edward S. Davidson
%A Gurindar S. Sohi
%A Joseph A. Fisher
%A Greg Grohoski
%A Yale Patt
%A James E. Smith
%A David R. Stiles
%T Better Than One Operation Per Clock: Vectors, VLIW, and Superscalar
%J Proc. 17th Annual Symposium on Computer Architecture, Computer
Architecture News
%I ACM
%V 18
%N 2
%D June 1990
%P 376
%K Panel Session
%X Panel lacked any "data-parallel," SIMD folk. Sorry, non-controversial.