moss@cs.umass.edu (Eliot Moss) (04/03/91)
In article <1991Apr3.074148.11109@cs.cmu.edu> vac@crux.fac.cs.cmu.edu (Vincent Cate) writes:
Now SPEC/MHZ, that is a ridiculous number. Does someone think that
all CPUs have the same number of gate-delays between pipeline stages?
MHZ is like MIPS, it just does not compare across architectures.
I think the point of the SPEC/MHZ numbers was not to give information for
purchasing decisions and the like, but rather to explore the effectiveness of
different instruction sets (and other architectural features) in obtaining
useful performance. This really does have to be normalized, since there is
skew in the marketplace in the maturity of technology used for different
available chips, etc. I would agree that MHz is not ideal since some designs
may have internal delays that make the achievable clock rate lower than for
other designs, but it is an interesting first cut comparison. You are right
that since SPEC is not a CPU benchmark, but rather a system benchmark that
includes I/O, that if one is interested in comparing CPU architecture and main
memory hierarchy (cache/bus implementation) one could come up with a better
benchmark that does not involve I/O.
--
J. Eliot B. Moss, Assistant Professor
Department of Computer and Information Science
Lederle Graduate Research Center
University of Massachusetts
Amherst, MA 01003
(413) 545-4206, 545-1249 (fax); Moss@cs.umass.edu