brian@neptune.AMD.COM (Brian McMinn) (03/19/87)
There was some vigorous (done with much arm waving) discussion in this news group a few weeks ago about the "optimum" size granularity for a register window. I couldn't say much then, but the Am29000 was announced Monday, so I can add my comments now. Contrary to what seemed to be a general consensus in that discussion, the Am29000 has no major speed problems with performing a full 7-bit add in the register access path. This allows us to address ALL 128 local registers without moving the stack pointer and gives us a minimum allocatable unit of ONE register (ie., the stack pointer can point ANYWHERE in the 128 local registers). How did we do it? 1) a well balanced pipeline, and 2) good circuit design. The 7-bit add did require some speed related circuit design, but the pipeline is balanced such there is no single speed limiting pathway. The whole chip hits its speed limit at about the same clock frequency. The Am29000 design team (based in Austin). -- Brian McMinn 1-(512)-462-5389 Advanced Micro Devices domainLand: brian@neptune.AMD.COM Austin, Texas bangLand: ...!amdcad!neptune!brian
amos@instable.UUCP (03/20/87)
I have just read the piece in Elctronics magazine; nice hype - they even have a picture of the (yet non-existent) chip. Hype aside, it looks like a compiler writer's dream - 192 registers! But then came the part about the 700ns context-switch time - that cannot include saving & restoring all registers, can it? If it doesn't, who amd how takes care of keeping track of who uses what and when? (I hope I'm making myself clear :-)) -- Amos Shapir National Semiconductor (Israel) 6 Maskit st. P.O.B. 3007, Herzlia 46104, Israel (011-972) 52-522261 amos%nsta@nsc.com 34.48'E 32.10'N
tim@amdcad.UUCP (03/21/87)
In article <722@instable.UUCP>, amos@instable.UUCP (Amos Shapir) writes: > I have just read the piece in Elctronics magazine; nice hype - they even > have a picture of the (yet non-existent) chip. Hype aside, it looks like > a compiler writer's dream - 192 registers! But then came the part about > the 700ns context-switch time - that cannot include saving & restoring > all registers, can it? If it doesn't, who amd how takes care of keeping > track of who uses what and when? (I hope I'm making myself clear :-)) The context switch time quoted was for the register bank model, where eight separate contexts can be stored on-chip. Each context has 16 general registers (which uses the local register set) and 8 registers used to save state information while the process is not running (processor status, Q register, etc.), stored in global registers. A context switch simply consists of saving the state information of the current process, restoring the state information for the next process, and changing the internal stack pointer to point to the new general register bank. -- Tim Olson Advanced Micro Devices (tim@amdcad)