albaugh@dms.UUCP (Mike Albaugh) (08/21/90)
I apologize ahead of time for the slightly commercial tone of this posting. I thought about it for four days before deciding to go ahead. I finally decided that it was at least as relevant as the various "is so, is not" debates after new benchmarks results are posted. A capsule summary, so you can decide whether to hit 'n': I have been involved in the design of a processor for my company's own use. It is targetted to "embedded systems" (no, really, more later) and we intend to use it in our own products. Someone way up the chain from me has asked whether there would be sufficient interest from others to bother offering it for sale outside the company. I know of few better places to ask than this newsgroup. OK, hit 'n' now if this is beyond the pale. Still here? Well, the chip in question is a 32-bit microprocessor That's 32-bit data, 32-bit addresses. Well, 30-bits come out as address lines and four data-strobes say what bytes we are using. I intended it from the start to be used in video games (That's what we make) and similar "embedded real-time" applications. In fact, the whole project arose from our frustration at attempting to shoe-horn "modern" microprocessors into the "embedded systems" we build. I want to distinguish this from the sort of processor which was designed for *nix workstations and got re-targetted as "for embedded systems" when it flopped. ASAP (The chip's name: Affordable Simplified-Architecure Processor) has been pretty carefully designed to not _preclude_ building a workstation (e.g. clean exceptions), but does not include an MMU or floating point (lost 30% of you right there, huh :-). You _could_ add them, but after adding a few meg of DRAM and a few hundred meg of disk, the cost of the CPU pretty much disappears. My intentions were: Running reasonably fast out of "grut" memory (4-5 MHz from EPROM) Possible to run faster out of faster memory, as the application could afford it or memory got faster/cheaper. (e.g. 12MHz @ 50ns) Straightforward to use, amenable to wide range of memory speed and debugging with Logic analyzers and scopes. This seems to often conflict with the goal of "speed at any price" Reasonably cheap. We are currently looking at about $20 US apiece in quantity. "Clean" in the sort of ways that lead to decent compiled code (I've re-targeted GCC) and non-rubber-room assembly language programming. Please no flames about assembly. The reality of _our_ systems is that there will always be some. In short, I had a mental picture of "A 6502 for the '90s", just as the 68000 was the 6502 of the '80s :-) I believe the resulting chip meets my criteria pretty well, but then, I also believe my kids are exceptional :-) If you feel that you may be interested in more info, please email, write, or call me. I don't want to be mass-emailing out the whole spec, as I feel that would be exceptionally rude to our uucp neighbors and probably violate our agreements with the vendor, but can flesh out the following sketch a bit. 29 general regs (32 - R0 (hard zero) - 2 for exceptions) Three-address ( reg <- reg op [reg or immediate] ) Load/store architecture, with 8/16/32 bit signed/unsigned data. Load and store are the only 2-cycle instructions, because the chip has a single data bus. Unaligned memrefs do _not_ automagically do two references, but they _do_ keep their mitts off un-addressed bytes and do something "reasonable". So external hardware _could_ trap on such references and "fix them up". Yes, delayed branches (one delay slot) both for speed and observability reasons. No mul/div hardware, but does have a barrel-shifter that even handles shifts by 32 :-) I have no idea what the spec-mark would be if I actually went ahead and build a *nix workstation with it in my "spare time" The actual (small) examples I have tried put it about 4-6 times as fast as a 68000 (what we use now) with the same memory. >>>>>>>>>>>> OF COURSE "Your mileage may vary" <<<<<<<<<<<< I will be embarking on an experiment to graft the processor onto an existing 68000-based board and get a realistic (though pesimistic) ratio for a whole system. The whole area of comparing such projects, where hardware _often_ mutates with the software makes spec look simple (sorry, mash :-) CMOS in a PLCC. What else would you like to know? Operators are standing by :-) Mike | Mike Albaugh (albaugh@dms.UUCP || {...decwrl!pyramid!}weitek!dms!albaugh) | Atari Games Corp (Arcade Games, no relation to the makers of the ST) | 675 Sycamore Dr. Milpitas, CA 95035 voice: (408)434-1709 | The opinions expressed are my own (Boy, are they ever)
nigel@modcomp.UUCP (Nigel Gamble) (08/22/90)
In <1142@dms.UUCP> albaugh@dms.UUCP (Mike Albaugh) writes: > In short, I had a mental picture of "A 6502 for the '90s" This has already been done, by Acorn Computers Ltd., of Cambridge, U.K. I think it's called the Acorn Risc Machine, and one of its design objectives was to be a 32 bit 6502-like CPU. I think it meets all of your other objectives, but there are others out there who can give you more information (are you listening, Roger Wilson (Acorn)?) Why not just use this chip, instead of re-inventing one of your own? -- Nigel Gamble uunet!modcomp!nigel MODCOMP, an AEG company modcomp!nigel@uunet.UU.NET 1650 W McNab Rd, Ft Lauderdale, FL 33340-6099