work@forum.SUBLINK.ORG (Andrea Gozzi @ Forum) (04/24/91)
Anyone can write about how the H1 (T9000) from INMOS is supposed to
run 150MIPS and 20MFLOPS? Architecture, clock, etc?
What's the degree of compatibility with T800?
Price?
Thanks in advance
Andrea Gozzi
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=========================== MODERATOR ==============================
Steve Stevenson {steve,fpst}@hubcap.clemson.edu
Department of Computer Science, comp.parallel
Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabellwork@forum.SUBLINK.ORG (Andrea Gozzi @ Forum) (04/24/91)
Anyone can write about how the H1 (T9000) from INMOS is supposed to run 150MIPS and 20MFLOPS? Architecture, clock, etc? What's the degree of compatibility with T800? Price? Thanks in advance Andrea Gozzi -- /////////////////////////////////////////////////////////////////////// / Andrea Gozzi - Via Campagnola 21/A - 42015 Correggio (RE) ITALY / / INTERNET: work@forum.sublink.org UUCP: ..rutgers!sublink!forum / / Fax ++39522692916 Ints:RayTracing-TeleCom-Music (Ensoniq Addicted) / ///////////////////////////////////////////////////////////////////////
cca04@seq1.keele.ac.uk (P.J. Mitchell) (04/25/91)
>From article <488@forum.SUBLINK.ORG>, by work@forum.SUBLINK.ORG (Andrea Gozzi @ Forum): > Anyone can write about how the H1 (T9000) from INMOS is supposed to > run 150MIPS and 20MFLOPS? Architecture, clock, etc? > What's the degree of compatibility with T800? The T9000 is supposed to be binary compatible with the T800 series of transputers. Doubtless there will be some subtle differences, but... > Price? Who knows, they don't actually exist yet (more's the pity). -- Paul Mitchell (CMA#86(18) MAG#65715 DoD#0145) | Physics Department, JANET: p.j.mitchell@uk.ac.keele.seq1 | Keele University, Keele, USENET: p.j.mitchell@seq1.keele.ac.uk | Staffordshire, ST5 5BG, U.K. BITNET: p.j.mitchell%seq1.keele.ac.uk@ukacrl | (+44 or 0)782 621111 ext 3966 -- =========================== MODERATOR ============================== Steve Stevenson {steve,fpst}@hubcap.clemson.edu Department of Computer Science, comp.parallel Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabell
vhs@britesun.radig.de (Volker Herminghaus-Shirai) (04/26/91)
Andrea Gozzi writes: >Anyone can write about how the H1 (T9000) from INMOS is supposed to >run 150MIPS and 20MFLOPS? Architecture, clock, etc? >What's the degree of compatibility with T800? >Price? A report in Markt&Technik magazine states that they have a 7 staged pipeline. The second stage acts as an instruction sorter (thus doing what could actually be done better by the compiler), rearranging instructions for parallel execution. It also states that they can execute a maximum of eight instructions at once in theis seven-staged pipeline (maybe including floating-point) and that more than half of the chips transistors is used up by their seperate 16KB I/D-cache(s). I do not remember any more details. -- Volker Herminghaus-Shirai (vhs@britesun.radig.de) panic: 80x86! Trying to vomit...
ccplumb@rose.waterloo.edu (Colin Plumb) (04/26/91)
vhs@britesun.radig.de (Volker Herminghaus-Shirai) wrote:
>It also states that they can execute a maximum of eight instructions at once
I haven't even seen it, but I'll bet money that what they mean is one
instruction and seven prefixes. On the trasnputer, all the instructions
have a 4-bit operand field. Larger operands are built up using prefix
instructions, which add their 4-bit operand field to the next "real"
instruction. Pushing this past one per cycle is pretty crucial to good
performance. I doubt they do more than one "real" instruction per cycle.
--
-Colinberg@marvin.e17.physik.tu-muenchen.de (Stephen R. van den Berg) (04/30/91)
If you guys can hold your breath for one week, then I'll have a data book on
the darn thing.
--
Sincerely, berg@marvin.e17.physik.tu-muenchen.de
Stephen R. van den Berg.
"I code it in 5 min, optimize it in 90 min, because it's so well optimized:
it runs in only 5 min. Actually, most of the time I optimize programs."edwardm@hpcuhe.cup.hp.com (Edward McClanahan) (05/04/91)
> The T9000 is supposed to be binary compatible with the T800 series of > transputers. Doubtless there will be some subtle differences, but... Backwards compatible... T800 compilers, etc... can be used to generate programs which will run on the T9000. The new T9000 does have some new instructions (as I understand)... =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Edward McClanahan Hewlett Packard Company -or- edwardm@cup.hp.com Mail Stop 42UN 11000 Wolfe Road Phone: (480)447-5651 Cupertino, CA 95014 Fax: (408)447-5039
davidb@brac.inmos.co.uk (David Boreham) (05/05/91)
In article <1991Apr26.053510.19231@watdragon.waterloo.edu> ccplumb@rose.waterloo.edu (Colin Plumb) writes: >vhs@britesun.radig.de (Volker Herminghaus-Shirai) wrote: >>It also states that they can execute a maximum of eight instructions at once > >I haven't even seen it, but I'll bet money that what they mean is one >instruction and seven prefixes. On the trasnputer, all the instructions >have a 4-bit operand field. Larger operands are built up using prefix >instructions, which add their 4-bit operand field to the next "real" >instruction. Pushing this past one per cycle is pretty crucial to good >performance. I doubt they do more than one "real" instruction per cycle. >-- > -Colin What ! Come on Colin, where's the smiley ? Seriously though, when the blurb says ``eight instructions'' it means ``eight operations''. Like an add, a branch, a FP operation, an address calculation and so on to eight if I could remember what they all are. The prefixing is dealt with by the instruction ``grouper'' and when we say ``eight instructions'' this does NOT include prefixes. I saw some press comment which mentions a forty-odd maximum instruction-per-cycle figure---this comes from counting prefixes and instructions folded into one operation by the grouper. The T9000 is a seriously fast machine and you could argue that the prefixing machanism used in the instruction set helps by cutting down on memory traffic compared with a RISC machine. David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos.com!davidb +44 454 616616 ex 547 | Internet: davidb@inmos.com
ccplumb@rose.waterloo.edu (Colin Plumb) (05/06/91)
I'd like to apologise for denying the achievements of the H1 (T9000) transputer development team. The transputer's 0 and 1-operand instructions and prefix instructions produce a native MIPS figure almost an order of magnitude larger than other processors, and this figure has been trumpeted in the past. If they can execute 8 "real" instructions in a cycle (peak), they've done something significant and praiseworthy. -- -Colin