dave@dtg.nsc.com (David Hawley) (05/08/90)
In article <AGLEW.90May7112551@dwarfs.csg.uiuc.edu> aglew@dwarfs.csg.uiuc.edu (Andy Glew) writes: [regarding ECC RMW penalties for doing partial writes] >But sometimes first-write exclusivity isn't desirable, and/or you want to be >able to do partial writes. >-- >Andy Glew, aglew@uiuc.edu Can a system be designed that never uses partial writes? How about only full-line reads and writes (on the far side of the cache from the CPU, that is)? Given the overhead that is often required for every transfer into and out of memory in a bus system, maybe it is more efficient to always transfer a full block of data and pay for the wasted cycles. When are partial accesses required, and how much does it cost to work around (or with) them? Are potential problems the result of required compatibility with existing hardware and/or software, or are they more fundamental? Tradeoffs? Just a bunch of partially-formed questions... Dave Hawley (dave@dtg.nsc.com)