zs01+@andrew.cmu.edu (Zalman Stern) (07/11/89)
As with all arguments about RISC vs. CISC, the latest compiler complexity argument is bogus because RISC and CISC are hardly monolithic categories. That is, there are characteristics that lean toward one camp or another and various chips use different combinations of these characteristics. Anyway, I would like some clarification on one specific point: > Excerpts from ext.nn.comp.arch: 11-Jul-89 Re: Compiling - RISC vs. CISC > David Trissel@oakhill.UU (2486) > The point was that RISC architectures DO require the pairing. Can you > name > any that don't? By "register pairing" I assume you mean instructions which take an even register specification and use the adjacent odd register as well. My perusal of the MIPS R2000 book indicates that there are no such instructions in that architecture. I believe this is also true of the AMD 29000. I think its almost true of the SPARC, but it has 64 bit load and store instructions from the integer unit's register file that utilize register pairing. (As I understand it the main reason these instructions were added to the SPARC was to speed up transferring register windows to/from memory. It is probably reasonable to write a compiler for SPARC that ignores these instructions and doesn't have to worry about register pairing.) The only place I could find register pairing in the 88000 was in the floating point instructions. This is a result of using one register file for the integer and floating point units. (My knowledge of the 88000 is limited, I have the user's manual, but I haven't read it in depth. I may be wrong about this...) Most other "RISC" chips I know of have separate integer and floating point register sets and avoid this problem. If my understanding of register pairing is incorrect, could you please post a correct definition. Also explain where this is going to come up in register allocation for a machine like the MIPS R2000. Sincerely, Zalman Stern Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890
burn@lpi.UUCP (Don Burn) (07/14/89)
In article <AYiW7Ha00Vs8MHnVob@andrew.cmu.edu> zs01+@andrew.cmu.edu (Zalman Stern) writes: >By "register pairing" I assume you mean instructions which take an even >register specification and use the adjacent odd register as well. My >perusal of the MIPS R2000 book indicates that there are no such >instructions in that architecture. I believe this is also true of the >AMD 29000. I think its almost true of the SPARC, but it has 64 bit load >and store instructions from the integer unit's register file that >utilize register pairing. (As I understand it the main reason these >instructions were added to the SPARC was to speed up transferring >register windows to/from memory. It is probably reasonable to write a >compiler for SPARC that ignores these instructions and doesn't have to >worry about register pairing.) > >The only place I could find register pairing in the 88000 was in the >floating point instructions. This is a result of using one register file >for the integer and floating point units. (My knowledge of the 88000 is >limited, I have the user's manual, but I haven't read it in depth. I may >be wrong about this...) Most other "RISC" chips I know of have separate >integer and floating point register sets and avoid this problem. Funny the AMD 29000 manual in front of me says: "By convention, a double precision floating-point operand is contained in two consecutive general purpose registers,..." The i860 manual states: "When accessing 64-bit floating-point or integer values, the i860 Microprocessor uses an even/odd pair of registers" I loaned out my SPARC manual but the compilers we implemented use register pairs, I don't know about MIPS but since it like SPARC used the Weitek chip set which uses register pairs I wouldn't be suprised if they have pairs exposed. Finally for a limited set of instructions (shifts) the IBM RT uses pairs. Don Burn Project Leader, Code Generator Group The opinions are my own, my company just gets the code.
khb@gammara.Sun.COM (gammara) (07/19/89)
In article <305@lpi.UUCP> burn@lpi.UUCP (Don Burn) writes: > >I loaned out my SPARC manual but the compilers we implemented use register >pairs, I don't know about MIPS but since it like SPARC used the Weitek chip ????? !!! All of the MIPSco machines I have seen used the R2010 or the R3010 which are certainly not like the Weitek chips. The MIPS chips are closely matched to the R2/3000 and have more clever algorithms than the Weitek chips. Keith H. Bierman |*My thoughts are my own. Only my work belongs to Sun* It's Not My Fault | Marketing Technical Specialist ! kbierman@sun.com I Voted for Bill & | Languages and Performance Tools. Opus (* strange as it may seem, I do more engineering now *)
mash@mips.COM (John Mashey) (07/20/89)
In article <116276@sun.Eng.Sun.COM> khb@sun.UUCP (gammara) writes: >In article <305@lpi.UUCP> burn@lpi.UUCP (Don Burn) writes: >> >>I loaned out my SPARC manual but the compilers we implemented use register >>pairs, I don't know about MIPS but since it like SPARC used the Weitek chip > >????? !!! All of the MIPSco machines I have seen used the R2010 or the >R3010 which are certainly not like the Weitek chips. The MIPS chips >are closely matched to the R2/3000 and have more clever algorithms >than the Weitek chips. The earliest MIPS M/500s (1986/1987) had CPU boards with sockets for R2010s, and an additional interface to a separate board (an R2360), which implemented the FP instructions using WTL 1164/65 & a bunch of logic. As soon as R2010s were available, that was the end of the R2360s, as R2010s were both much faster and much cheaper. R2360s stopped shipping mid-1987, and most people upgraded their M/500s quickly with R2010s anyway, which is why khb probably would not have seen the older boards. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086