[comp.arch] VISC - speeding up moto cisc mpu's?

abaum (Allen Baum) (05/20/91)

>I think it would be more in line with RISC philosophy to rip out as
>much of the CISC core as possible, leaving close to the bare minimum of 
>what is needed to emulate via software traps those addressing modes that 
>would be deleted (most) and those instructions that would be deleted 
>(anything that compilers are staying away from, up to the neck of the 
>curve).
>
>This is how many FPU ops in the 68040 are implemented, and the strategy 
>seems to have been successful, if SPEC numbers are worth their salt.  

Actualy, there are several reasons the '040 SPEC numbers are better-

1- faster clock, resulting from better process technology,
2- better compilers
3- tightly integrated FPU (means less cycles wasted on instruction
  decoding & overhead as opposed to computation
4- better FPU - fewer cycles needed for ops that are used.

While ripping out the unneeded stuff may contribute to 1, and to 4,
you may find the bulk of the differences don't; i.e. if you put in
all those CISCy ops, it wouldn't run significantly slower.

All that, of course, presupposes that (a) you can fit this expanded
function on the chip, and (b) you would have finished debugging it
before you ran out of development funds. This, to my mind, is the
really big win for RISC, and virtually guarantees a speed advantage.

clc5q@hemlock.cs.Virginia.EDU (Clark L. Coleman) (05/20/91)

In article <177@armltd.uucp> abaum (Allen Baum) writes:
>
>Actualy, there are several reasons the '040 SPEC numbers are better-
>
>1- faster clock, resulting from better process technology,

This does not make any sense to me. The only released SPEC numbers for
the 68040 are for 25MHz chips. There are 68030 chips running at 25MHz
for several years now, and likewise for the 68882 FPU that went with
the 68030. Any improvement in SPEC numbers over the 68030 did not come
from the 68040 having a faster clock rate.

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