csimmons@hqpyr1.oracle.UUCP (Charles Simmons) (01/13/89)
So, I'm sitting around one day porting some code to a MIPS R2000 processor, and suddenly I realize that I need a "test-and-set" instruction. Soon thereafter, I realize that the MIPS R2000 doesn't seem to have anything remotely resembling a read-modify-write instruction. (For my application, I can't inhibit interrupts, because I'm running in user mode.) So... a few questions arise. Some people around here find it hard to believe that a recently designed architechture doesn't have instructions for multiprocessor synchronization. Of course, these same people refuse to use any hardware that doesn't have at least 16 processors. For myself, I kind of started wondering what would happen if I started up a multiply instruction, and then did a load/nop/add/store squence of instructions while waiting for the multiply to complete. I looked into my reference manual (_MIPS R2000 RISC Architechture_ by Gerry Kane), and noticed that this small area wasn't talked about real well. So... What happens when the R2000 is executing a multiple cycle instruction (i.e. multiply or divide), and an interrupt, system call, or page fault occurs? Hmmm... I suppose the simplest implementation would be to do nothing special, and let the multiply or divide complete while the current context is being saved. Most likely, the multiply or divide will complete before getting around to saving HI and LO. So, I guess my questions are: 1) How much did the MIPS architechts worry about multiprocessor configurations, and why did they decide not to implement some sort of synchronization primitive? 2) Is there any real cute kludge anyone can suggest for faking something that would act like an interlocked instruction? Thanks, Chuck
garner@gaas.Sun.COM (Robert Garner) (01/14/89)
> So, I'm sitting around one day porting some code to a MIPS R2000 > processor, and suddenly I realize that I need a "test-and-set" > instruction. Soon thereafter, I realize that the MIPS R2000 > doesn't seem to have anything remotely resembling a read-modify-write > instruction. Note that SPARC, "a recently designed architecture", has two synchronization primitives: SWAP exchanges a memory location with a processor register and "load-and-store-unsigned-byte", LDSTUB, is your basic "test-and-set". Despite not being an IBM "compare-and-swap," SWAP is a relatively powerful primitive. As an example, it can be used to do a parallel enqueue operation to the tail of a linked list without using an explicit semaphore. (The presence of NIL in the list is used to block other processes.) Although I am not an MP-expert, compare-and-swap is apparently difficult to use "safely". - Robert Garner p.s. Marketing lives on! There's a new magazine called: MIPS: The Magazine of Intelligent Personal Systems
earl@wright.mips.com (Earl Killian) (01/15/89)
In article <557@oracle.UUCP>, csimmons@hqpyr1 (Charles Simmons) writes:
<<questions about mp synchronization and multiply/divide>>
The MIPS R2000 and R3000 do not have special instructions for
multiprocessor synchronization. When the R2000 was being designed,
anything that wasn't going to be used, or wasn't fully understood was
left out, to be added later, when it could be developed in tandem with
the system and software. The classical "test-and-set" or equivalent
was explicitly omitted, especially after consultation with various
people who had serious MP experience:
a) No one (or even two or three) of the classic synchronization
operations made all MP designers happy. Many of them expected
to add substantial synchronization hardware in any case.
It was thus clear that we did not have a solution available at
the time that was sufficient, and as usual, we don't put things
in there that we're not sure are the right things.
b) A traditional test-and-set complexifies the design, which
would be OK if you thought it was THE solution. However,
especially for serious high-performance MP's, any construct
that really wants to lock the bus is a no-no anyway.
To do read-modify-write operation on the VME bus, MIPS cpu boards
support locations that can be set that cause the next VME reference to
hold the bus, so you can do:
store to magic location
VME load
update
VME store
reset magic location
This service is available only to the Kernel.
Some of multiprocessor systems based on the R2000/R3000 implement
memory mapped locations that can be used by user programs for
synchronization.
In the future when MIPS does multiprocessing (which means chips,
systems, os, and compilers), we might do it by adding instructions.
Or we might not.
I'm not sure what the multiply/divide instructions have to do with
mp. After executing a MULT or DIV instruction, the hardware churns
away while you execute new instructions. If you execute a MFLO or
MFHI to read the multiply/divide result, the hardware interlocks and
waits. If you take an exception, the hardware churns away as usual
(the multiply/divide has committed after all). It the exception
handler executes a MFLO or MFHI, it interlocks as usual.
--
UUCP: {ames,decwrl,prls,pyramid}!mips!earl
USPS: MIPS Computer Systems, 930 Arques Ave, Sunnyvale CA, 94086mash@mips.COM (John Mashey) (01/15/89)
In article <85346@sun.uucp> garner@sun.UUCP (Robert Garner) writes: ... >p.s. Marketing lives on! There's a new magazine called: > > MIPS: The Magazine of Intelligent Personal Systems No connection with MIPS Computer Systems; the lawyers have already been having discussions, I believe, regarding confusion-avoidance. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
mash@mips.COM (John Mashey) (01/18/89)
In article <11200@winchester.mips.COM>, mash@mips.COM (John Mashey) writes: > In article <85346@sun.uucp> garner@sun.UUCP (Robert Garner) writes: > ... > >p.s. Marketing lives on! There's a new magazine called: > > > > MIPS: The Magazine of Intelligent Personal Systems > No connection with MIPS Computer Systems; the lawyers have already been > having discussions, I believe, regarding confusion-avoidance. I'd heard there was such a thing, but I obviously hadn't seen what Robert was referring to, but just yesterday got my home mail sorted out after traveling about, and what was there, but an envelope that said: "Are you ready for the 80486? The 88000? The next generation? MIPS is, and you can be too...for FREE. Details inside." Hmmm, must be free advertising, a bit inadvertent, perhaps. :-) -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086