mark@mips.COM (Mark G. Johnson) (01/01/89)
The SPARC instruction set (hence the "architecture", not a particular "implementation") includes opcodes for manipulating IEEE-standard 80-bit and 128-bit floating point numbers. As I recall, the IEEE standard calls them double-extended (80b) and quad (128b). The MIPS instruction set includes them too. However, in the current 16.7 MHz implementations of SPARC and MIPS, these longer-precision instructions are not executed directly in hardware. They trap, and the requested operation (128-bit divide etc) is done by software. We did a weird thing :-) at MIPS with these instructions. Whenever one of these instructions is encountered, the trap handler emulates the instruction, AND it does something else. :-) It instructs the console maintenance processor to activate its remote-diagnostics modem, which dials a special phone number back at the factory, here at MIPS. In fact it dials a phone which sits on my desk :-). The maintenance processor logs the date and time, the serial number of the machine, and the type of longer-precision operation that was requested :-). So far, in over 2 years, the phone has never rung. :-) Thus it is tempting to conclude that user programs do not suffer a serious performance degradation from emulating longer-precision (80 and 128 bit) floating point operations in software :-). -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 ...!decwrl!mips!mark (408) 991-0208