dsc@raspail.UUCP (Dave Christie) (01/04/89)
If one can believe performance numbers in advertisements, then
SPARC @ 30ns == R3000 @ 40ns
which, IMHO, implies that MIPS is the better architecture.
I am referring to recent Gazelle ads (Dec 12 EE Times p.T80 is one)
which imply that a SPARC running at 33 MHz will achieve 20 mips
(and needs GaAs support to do that! - not a bad argument for on-chip
MMU and cache control). The M2000 @25MHz has been rated at 20 vax mips,
by MIPS anyway - but from what I've seen of their performance briefs they
do a reasonable job of benchmarking. Granted, the ad does not even
say what kind of mips (vax or sparc - I would hope vax!), much less
what sort of benchmarks this figure comes from, or cache sizes, etc, etc.
But people do tend to put their best foot forward in advertising, no?
Does anyone know where such a figure might have come from? Is it maybe
a product of the SPARC Vendor's Council? An official SUN position?
--
Dave Christie, Control Data Canada, Mississauga, Ontario
dsc@raspail.UUCP or {backbone}!uunet!rosevax!shamash!raspail!dsc
"Any opinions expressed herein do not necessarily reflect those of CDC,
and for that matter, probably no one else."walter@garth.UUCP (Walter Bays) (01/05/89)
>If one can believe performance numbers in advertisements, then
...one can also believe Isuzu commercials :-)
--
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My opinions are my own. Objects in mirror are closer than they appear.
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------------------------------------------------------------------------------aglew@mcdurb.Urbana.Gould.COM (01/06/89)
>If one can believe performance numbers in advertisements, then > > SPARC @ 30ns == R3000 @ 40ns > >which, IMHO, implies that MIPS is the better architecture. ^^ implementation ^ I am probably sticking my foot in it, but isn't MIPs double clocked? But then, SPARC probably is, too.