brian@neptune.AMD.COM (Brian McMinn) (09/04/87)
In article <300@ma.diab.UUCP> pf@ma.UUCP (Per Fogelstrom) writes: >In article <18102@amdcad.AMD.COM> tim@amdcad.UUCP (Tim Olson) writes: >>The Am29000 has Master/Slave mode operation, where two processors >>operate in lock-step. The Slave processor checks all of the master's >>outputs against the slave's internal values cycle by cycle, and signals >>an error (MSERR) if there is a discrepency in any value. > >Question: What effect has this function on performence ? Internal to the 29000, there is no effect whatsoever on performance. The master/slave checking is done in hardware with no speed penalty. (We paid a little area for it.) From a system standpoint, there is a monetary cost to put one (or more) extra 29000's on the board, wire them up, and provide error recovery logic. The extra capacitive loading placed on the external signal lines may slow the system down, but only if the capacitive loading specifications are exceeded (which isn't very likely for one or two slave 29000's). You want real numbers? Well... no-one has built such a system yet, but I'd be surprised if there were any speed penalty at all. -- Brian McMinn 1-(512)-462-5389 Advanced Micro Devices domainLand: brian@neptune.AMD.COM Austin, Texas bangLand: ...!amdcad!neptune!brian