ken@sci.UUCP (Ken Karakotsios) (06/19/87)
There has been some talk that simulation will sink all the MIPs
that can be thrown at it for a long time to come. I would tend to agree
with that. I have recently finished a microprocessor design (120K
transistors) which was simulated on VAXes of various sizes, from
micro-vax to 8650. Overall we simulated 2 real seconds of a 25MHz CPU's
time in about 15+ million seconds (6 months) of CPU time. This means that
the simulation was a factor of 7+ million slower than the actual hardware.
You may say that I needed a faster machine, but I could have been
designing a faster, and a bigger, processor. You may also say that I could
have simulated fewer cases, or at a higher level. However, we had on-board
floating point and needed to test all the corner cases. Also simulating at
a higher level might have caused us to miss some of the bugs in our microcode.
You might also very well suggest that I buy a simulation accellerator,
but what if I am designing a simulation acellerator? It seems that software
simulation of hardware will never be fast enough if you are trying to design
the next generation of hardware. Someone else mentioned that it may just be
a vicious cycle, where we are only designing faster computers so that someone
else will buy them to design the *next* generation of computers. Perhaps the
only solution will be simulation accellerators built out of EPLDs, where
any array of electrically programmable gate arrays is configured to become
the hardware you are simulating. This kind of sounds like breadboarding all
over again, doesn't it? An interesting question is, if we could simulate
something (a digital machine) efficiently enough (at a low enough cost and
a high enough performance) would we actually need to build it, or could we
just sell the simulation model running on the hardware simulator?
Ken Karakotsios {sci!ken}
Silicon Compilers System Corp
The ideas and opinions expressed here are only mine, and do not
reflect the opinions or policies of Silicon Compiler Systems Corp.josh@polaris.UUCP (Josh Knight) (07/01/87)
In article <6176@sci.UUCP> ken@sci.UUCP (Ken Karakotsios) writes: > > There has been some talk that simulation will sink all the MIPs >that can be thrown at it for a long time to come. I would tend to agree >with that. Doesn't it seem that this is an arena for special purpose architectures, perhaps like the YSE or other approaches? See "The IBM Yorktown Simulation Engine" (G.F. Pfister, Proc. IEEE, Vol. 74, No. 6, pp. 851-860) for a description and a fair number of references. Although it's fairly old hardware, the article claims a 600-2000 fold speed up over the simulation rate of a general purpose processor (IBM 370/168). It seems like logic simulation is an area with enough inherent parallelism so that using a traditional SISD machine is just not the right thing to do. Of course these are only my opinions, not my employers. -- Josh Knight, IBM T.J. Watson Research josh@ibm.com, josh@yktvmh.bitnet, ...!philabs!polaris!josh