david@elroy.jpl.nasa.gov (David Robinson) (02/23/90)
What are the limits of moving existing architectures such as SPARC and
MIPS towards super-scalar and maintaining binary compatibility?
A simplistic approach would be to simply fetch 2 or more instructions
at once and decode/dispatch them in parallel if possible. Existing
binary code would probably not be optimal but would probably work.
New compilers with better scheduling algorithms could take advantage
the the new parallelism.
I sounds simple so I must be missing something or are existing "RISC"
architectures going to have to change substantially if they want to
get into the super-scalar game? (Assuming they want to)
-David
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