nelsn@houxj.UUCP (M.NELSON) (06/12/87)
It has been a few months since NCR announced their first microprocesser
based multiprocessor (NCR Tower 32/800).
Has anyone seen it yet ? Is there any
benchmark data available yet ?
From the sales literature I have, it is a Multibus II based
message passing multiprocessor and it does not have any shared memory.
Could anybody shed some light on how shared memory is supported in the system
(under UNIX). How does the operating system work ?
How does it do load balancing ? How about message passing ?
Is it the way to go ?
Any other comments are appreciated.
Thanks.
--
Matthew Nelson
AT&T Information Systems
ihnp4!houxj!nelsn
nelsn@houxj.ATT.COMalvitar@madhat.UUCP (Phil Harbison) (06/14/87)
In article <220@houxj.UUCP>, nelsn@houxj.UUCP (M.NELSON) writes: > It has been a few months since NCR announced their first microprocesser > based multiprocessor (NCR Tower 32/800). Has anyone seen it yet ? Is > there any benchmark data available yet? See "Inside Edge", page 21 in the June issue of UNIX/World. The 32/800 is a multiprocessor system based on the MC68020. That article lists the performance of various NCR systems relative to the performance of the Mini-Tower. A 32/800 with 4 Applications Processors (APs) has a rela- tive performance of 14.4. A single AP configuration has a performance of 4.5. > From the sales literature I have, it is a Multibus II based message > passing multiprocessor and it does not have any shared memory. Could > anybody shed some light on how shared memory is supported in the system > (under UNIX). How does the operating system work? How does it do load > balancing? How about message passing? The 32/800 uses both Multibus-I and Multibus-II. The logical address space for each process is 4-Gbytes, split evenly between user and kernel space. The kernel space is further split into 64 subspaces of 32-Mbytes each. One subspace is allocated for each AP, and one space is divided among the I/O processors (1-Mbyte each); therefore, any AP can address the space of any other AP or I/O processor. Dynamic load balancing is implemented by assigning each new process to the least-loaded AP. A static load balancing daemon reads the load status of all APs and may redistribute processes. When a process must be moved to another AP, the new AP copies only the minimum user structs and relies on normal paging to do the rest. The AP has a 16.7MHz 68020, supported by a 68881 FPU, an MMU, an 8-Kbyte instruction cache and a 2-Kbyte data cache. The I cache uses virtual addresses, while the D-cache uses physical addresses. The MMU is based on the 68861, a gate-array that uses an off-chip translation cache to implement a subset of the 68851 PMMU features. The translation cache is split between 512 kernel entries and 512 user entries, implemented in 30 nanosecond static RAM. Each AP can have up to 16-Mbytes of memory on a private bus. Each processor other than the AP has 1-Mbyte of private RAM. There are Termincal Processors (TP), File Processors (FP), Communications Pro- cessors (CP), and a LAN Processor (LP). The FP contains two 68010s, one to handle file system code and one to handle physical I/O. The TP is similar with one 68010 handling the eight ports and one executing kernel code. The CP supports two synchronous ports, with a 68010 executing driver and protocol code, and an 8085 handing the device interrupts. The LP has a 68010 executing kernel code, while an 80186 and 82586 handle the Ethernet. Enough plagiarism! :-) For more info, consult UNIX/World. -- Live: Phil Harbison USPS: 3409 Grassfort Drive, Huntsville, AL 35805-5421 Uucp: {clyde,uunet}!madhat!alvitar Bell: 205-881-4317
wingard@ncrcae.Columbia.NCR.COM (Steve Wingard) (06/15/87)
In article <219@madhat.UUCP> alvitar@madhat.UUCP (Phil Harbison) writes: > >The 32/800 uses both Multibus-I and Multibus-II. The logical address >space for each process is 4-Gbytes, split evenly between user and kernel >space. The kernel space is further split into 64 subspaces of 32-Mbytes >each. One subspace is allocated for each AP, and one space is divided >among the I/O processors (1-Mbyte each); therefore, any AP can address >the space of any other AP or I/O processor. > Just to clarify a point -- the Tower 32/800 does NOT use Multibus I. Processor modules have two interfaces on them: the Multibus II interface which connects the processor to the rest of the system and a proprietary interface to the processor's local memory. Steve Wingard ...!ucbvax!sdcsvax!ncr-sd!ncrcae!wingard NCR Corp., E&M-Columbia ...!decvax!mcnc!ncsu!ncrcae!wingard wingard@ncrcae.NCR.COM