cs450edf@iitmax.UUCP (edward federmeyer) (04/15/88)
I have a question that may seem dumb and obvious, but remember: 'The only dumb question in the unasked question...' So, I have read ALOT of ads in for example Computer Shopper and other computer mags that mention "0 Wait State" and "1 Wait State". What do they mean by these terms? I have never seen even a short blurb describing what they mean, and noone I've talked to yet knows. This SEEMS to be a term that everyone had heard, but never found out what it really means! If you are one of these advertisers, or hey, even if your not, and know what these terms mean, please send a reply. I have a whole other boatload of people who would like to know also. By the way, which is better? "0" or "1" (or "2") wait state design? Ed Federmeyer
sarathy@gpu.utcs.toronto.edu (Rajiv Sarathy) (04/21/88)
In article <1005@iitmax.UUCP> cs450edf@iitmax.UUCP (edward federmeyer) writes: > >... >'The only dumb question in the unasked question...' > >So, I have read ALOT of ads in for example Computer Shopper and other >computer mags that mention "0 Wait State" and "1 Wait State". What do >they mean by these terms? ... >... >Ed Federmeyer A 'wait state' is the number of clock cycles that a computer must wait before proceeding with the next instruction. This wait occurs at different frequencies on different machines. While waiting, the computer refreshes RAM. Naturally, 0 wait-state means that the architecture of the motherboard allows software to run uninterrupted even when the computer is refreshing RAM (fastest), and 2 wait-states mean that the software which is currently being run must wait for a few nanoseconds (slower). However the buyer mustn't judge two computers based solely on wait-states. For instance, a 16MHz machine with 0 wait-states is going to be much slower than a similarly equipped 25MHz machine with 2 wait-states. Raj Sarathy, Undergraduate, University Of Toronto, Department of Computer Science
root@mfci.UUCP (SuperUser) (04/21/88)
In article <1988Apr20.195805.25922@gpu.utcs.toronto.edu= sarathy@gpu.utcs.UUCP (Rajiv Sarathy) writes: = =In article <1005@iitmax.UUCP= cs450edf@iitmax.UUCP (edward federmeyer) writes: == ==... =='The only dumb question in the unasked question...' == ==So, I have read ALOT of ads in for example Computer Shopper and other ==computer mags that mention "0 Wait State" and "1 Wait State". What do ==they mean by these terms? ... ==... ==Ed Federmeyer = =A 'wait state' is the number of clock cycles that a computer must wait before =proceeding with the next instruction. This wait occurs at different frequencies =on different machines. = =While waiting, the computer refreshes RAM. Naturally, 0 wait-state means that =the architecture of the motherboard allows software to run uninterrupted even =when the computer is refreshing RAM (fastest), and 2 wait-states mean that the =software which is currently being run must wait for a few nanoseconds (slower). = =However the buyer mustn't judge two computers based solely on wait-states. For =instance, a 16MHz machine with 0 wait-states is going to be much slower than a =similarly equipped 25MHz machine with 2 wait-states. = =Raj Sarathy, Undergraduate, =University Of Toronto, Department of Computer Science Whoa there, Raj. That's no definition of wait-states that I've ever heard. A wait-state is a clock cycle that the cpu spends stalled because it needs a memory operation to complete before it can continue, and main memories of any decent size are always slower than the cpu. Suppose your micro kicks off a memory load, and suppose that transferring the address to memory, performing the memory access, and returning the results takes the equivalent of 4 cpu clock cycles. The cpu will have nothing to do after sending out the request, so it must wait until the memory finishes the access. There are many other nuances to this, and every manufacturer does this a different way (there are even ways of getting real work done during the waits), but wait-states have nothing to do with refresh. Bob Colwell mfci!colwell@uunet.uucp Multiflow Computer 175 N. Main St. Branford, CT 06405 203-488-6090
bcase@Apple.COM (Brian Case) (04/22/88)
In article <1988Apr20.195805.25922@gpu.utcs.toronto.edu> sarathy@gpu.utcs.UUCP (Rajiv Sarathy) writes: > >In article <1005@iitmax.UUCP> cs450edf@iitmax.UUCP (edward federmeyer) writes: >>So, I have read ALOT of ads in for example Computer Shopper and other >>computer mags that mention "0 Wait State" and "1 Wait State". What do >>they mean by these terms? ... >A 'wait state' is the number of clock cycles that a computer must wait before >proceeding with the next instruction. > >While waiting, the computer refreshes RAM. Naturally, 0 wait-state means that >the architecture of the motherboard allows software to run uninterrupted even >when the computer is refreshing RAM (fastest), and 2 wait-states mean that the >software which is currently being run must wait for a few nanoseconds (slower). Omygod, the blind leading the blind. Refresh is not the cause of wait states. Wait states happen when the minimum memory access time is too slow to allow the processor to proceed after a memory access is requested. The name "wait state" is pretty much a hold-over from the earliest days of micro- procesors; anyone remember counting "T-states" on the i8080? So, a wait state occurs when the microprocessor must wait for the memory to finish satisfying an access request; in such a case, the memory control logic and/or the microprocessor go into a "wait state." So, if the memory is fast enough to satisfy a request without causing the microprocessor to wait at all, it is popularly referred to as a "0-wait state" design, if one wait state must be inserted after a memory request, they call it a "1-wait state" design, etc. Note that with more modern microprocessors, the fact that memory is "slower than the microprocessor" might matter much less due to overlap between instruction execution and memory access. Even the 68020 can do this to a degree on memory writes. >However the buyer mustn't judge two computers based solely on wait-states. For >instance, a 16MHz machine with 0 wait-states is going to be much slower than a >similarly equipped 25MHz machine with 2 wait-states. Your warning is correct, but your example is quite possibly wrong. I would wager that the 16 MHz 0-wait state design is the same as the 25 MHz, 2-wait state design. In fact, if you read and believe the advertisements of the PC clone makers, a 10 MHz, 0-wait state design is as fast as a 12 MHz, 1-wait state design, a 12-MHz, 0-wait state design is as fast as a 16 MHz, 2-wait state design, etc. Clearly, the validity of such claims depends on a factors such as the program being run and the microprocessor in question (8088, 8086, 80286, 80386). Hope this helps the original question-asker.
farren@gethen.UUCP (Michael J. Farren) (04/22/88)
sarathy@gpu.utcs.UUCP (Rajiv Sarathy) writes: > >In article <1005@iitmax.UUCP> cs450edf@iitmax.UUCP (edward federmeyer) writes: >>"0 Wait State" and "1 Wait State". What do they mean by these terms? ... > >A 'wait state' is the number of clock cycles that a computer must wait before >proceeding with the next instruction. > >While waiting, the computer refreshes RAM. Close, but no cigar. If the access time of a memory system (the time it takes for valid data to appear at the outputs after a valid address has been presented to the inputs) is longer than the time which the processor requires the data to be present, the processor has to wait, with its memory circuits idle, until the data are there. A wait state is simply a measure of that time, usually a multiple of the clock speed. If, for example, your memory takes 500 nanoseconds to produce valid data, but the processor, running at 10 MHz, expects the data to be present after 400 nanoseconds, the processor will wait one clock cycle (100 ns), and so that particular memory will impose one wait state. During this time, memory is typically NOT being refreshed - it's busy, it can't be bothered with that refresh stuff. Refresh takes place as a seperate operation (although snazzily designed memory systems can make this process nearly invisible to the processor), and usually requires most of an entire memory cycle. -- Michael J. Farren | "INVESTIGATE your point of view, don't just {ucbvax, uunet, hoptoad}! | dogmatize it! Reflect on it and re-evaluate unisoft!gethen!farren | it. You may want to change your mind someday." gethen!farren@lll-winken.llnl.gov ----- Tom Reingold, from alt.flame
gillies@uiucdcsp.cs.uiuc.edu (04/26/88)
There should be a more precise metric for machines with caches that
achieve zero wait-states. For instance, if your machine is
Wait State When How often
0 in the cache 97% of the time
2 not in the cache 3% of the time
Then I submit you are using a .06 wait-state machine. The expected
value of the number of wait-states per memory reference is .06. The
cache hit ratio should be computed by running a dhrystone benchmark
compiled in C, or some other "universal" benchmark. Now maybe we can
get the PC companies to agree on this standard.....
Don Gillies {ihnp4!uiucdcs!gillies} U of Illinois
{gillies@p.cs.uiuc.edu}yueh@cse.usc.edu (Alan Yueh) (04/27/88)
In article <76700023@uiucdcsp> gillies@uiucdcsp.cs.uiuc.edu writes: > >There should be a more precise metric for machines with caches that >achieve zero wait-states. For instance, if your machine is > >Wait State When How often >0 in the cache 97% of the time >2 not in the cache 3% of the time > >Then I submit you are using a .06 wait-state machine. The expected >value of the number of wait-states per memory reference is .06. This metric is currently being used. Both the Compaq 386/20 and the IBM PS2 Model 80-111 (also 20Mhz) have a rated wait state of 0.8 (or is it 0.6? I forgot.) I'm quite sure that IBM releases the fractional figure, I don't know if Compaq does as well. However, lest I get flamed for mistaking the PS2 structure, let me say the Model 80 does not get the fractional wait state figure from cache miss/hit ratios: rather it is a function of accessing the memory within the same 2K page. (OK, so it looks like a cache without the separation of hardware.) However, the publishing of the fractional wait states begs the question: what's the benchmark that would reference a common 2K page? I suppose that's like the benchmark that determines a cache hit ratio. Anyway, I don't know the benchmarks that IBM and Compaq used to ascertain the wait states. Regards, A.W.Yueh (alan) (soon to be "formerly yueh@cse.usc.edu")