[comp.arch] Strange cache addressing algorithm

drw@laurent.mit.edu (Dale R. Worley) (11/06/90)

The Intel i860 uses a strange algorithm for deciding which line in the
cache to assign a particular memory address.

I remember reading an article in the last year or so that argued that
the usual low-n-bits-of-the-address algorithm was susceptible to bad
performance (especially if you referenced only every n-th byte of
memory) and discussed a hashing (?) algorithm for assigning cache
lines to addresses.  Does anybody remember where this was published?

Thanks,

Dale
drw@math.mit.edu