sritacco@hpdmd48.boi.hp.com (Steve Ritacco) (01/31/91)
Ok, now that EE times ran a cover article on the R4000, is it official? Anyone care to give more details if it is official. How many stages in the pipeline? What is the organization of the on chip caches? What is the second level cache control like? How many entries in the TLB, and is it the same structure as the R3000? What is the "multi-processor" support like? How many cycles for an integer multiply and divide? How about the cycle counts for the FP operations? Is the floating point unit super-piplined too?
cprice@mips.COM (Charlie Price) (02/02/91)
In article <14900023@hpdmd48.boi.hp.com> sritacco@hpdmd48.boi.hp.com (Steve Ritacco) writes: >Ok, now that EE times ran a cover article on the R4000, is it official? >Anyone care to give more details if it is official. I have posted the 1-Feb press release about the R4000 to comp.sys.mips. This is NOT a *product* announcement, it is more in the nature of a technology disclosure. I would *like* to tell you more about it, but I can't say more until a product announcement (and no, I can't tell you when that will be (if I knew (which I don't))). I'm sure this is most unsatisfying, but go read the press release and you will get the details that the company is willing to divulge. To put a pinch of technical content into this posting... The most interesting thing (details, of course, in the future) is probably that the R4000 is a 64-bit machine but will run existing 32 bit binaries. -- Charlie Price cprice@mips.mips.com (408) 720-1700 MIPS Computer Systems / 928 Arques Ave. / Sunnyvale, CA 94086-23650
grunwald@foobar.colorado.edu (Dirk Grunwald) (02/02/91)
I had heard rumour of performance ranges in the 80->100 mips range, about 4x the current performance. If the R4000 has a 64 bit ALU/data bath, could it execute two insns in the same ALU, just not propogating e..g, the carry information? This would give you 2 (super pipelined) * 2 (superscalar) performance. Likely?
mslater@cup.portal.com (Michael Z Slater) (02/03/91)
>Ok, now that EE times ran a cover article on the R4000, is it official? >Anyone care to give more details if it is official. > >How many stages in the pipeline? Eight. I-cache and D-cache are divided into two stages each, and a tag-check stage is added after the two D-cache stages. Otherwise, similar to R3000. >What is the organization of the on chip caches? Direct-mapped, copy-back, 8 K bytes each. >What is the second level cache control like? Just hook up synchronous SRAMs. 128-bit-wide interface. Full ECC, with detection in HW and correction in SW. Direct-mapped, copy back. Cache size 128K to 4M. >How many entries in the TLB, and is it the same structure as the R3000? 96 entries in pairs (i.e., 48 pairs). Structure is different to support multiprocessor stuff. Also, page size is selectable on a per-entry basis from 4K to 16M. >What is the "multi-processor" support like? Way too complex for me to explain. It supports snooping and directory-based coherency protocols. Cache tags include status bits for shared, exclusive, etc . TLB includes bits for coherent, non-coherent, write update, write invalidate. The chip provides the mechanisms, but not the policy; an external bus interface chip must provide the rest. >How many cycles for an integer multiply and divide? Multiply is half the cycles of an R3000, divide is the same. >How about the cycle counts for the FP operations? Mostly the same as for R3000; multiply is 25% faster. Of course, all are faster because of higher clock rate. (Note cycle count is based on cycles of the 50-MHz external clock, not 100-MHz internal clock, so speedup is by a factor of 50/33, not 100/33, comparing to a 33-MHz R3000/3010.) >Is the floating point unit super-piplined too? I think this gets into a semantic issue. If superpipelined means a single logical operation is divided into more than one pipeline stage, then I think all FPUs that are pipelined are "superpipelined". A small plug: the 2/6/91 issue of Microprocessor Report has what I expect will be the most detailed article on the R4000 available until the full announcement . Michael Slater, Editor and Publisher, Microprocessor Report mslater@cup.portal.com 707/823-4004 fax: 707/823-0504
cprice@mips.COM (Charlie Price) (02/05/91)
In article <1991Feb2.022443.12818@csn.org> grunwald@foobar.colorado.edu writes: > >If the R4000 has a 64 bit ALU/data bath, could it execute two insns in >the same ALU, just not propogating e..g, the carry information? This >would give you 2 (super pipelined) * 2 (superscalar) performance. > >Likely? The R4000 is not superscaler. You can combine superscaler logic with superpipelined functional units, but the amount of instruction-level parallelism that is available limits the benefit. My limited-information take on this is that there isn't enough space available on chips in the next couple years to make a single-chip combined superscaler/superpipelined processor a win. Instead, folks will stick with their basic execution unit, superscaler or superpipeline, and add more on-chip cache as more on-chip gates are possible. -- Charlie Price cprice@mips.mips.com (408) 720-1700 MIPS Computer Systems / 928 Arques Ave. / Sunnyvale, CA 94086-23650
glew@pdx007.intel.com (Andy Glew) (02/06/91)
..> The R4000 will have 64 bit integers and addresses... How many bits are in a "long"? How many bits are in an "int"? How many bits are in a "void *"? Are there "long long"s? Are there "void long *"s? How many "compiler memory models" are there? -- Andy Glew, glew@mipon2.intel.com Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway, Hillsboro, Oregon 97124-6497