andy@carcoar.Stanford.EDU (Andy Freeman) (07/09/88)
In article <11474@steinmetz.ge.com> oconnor%sungod@steinmetz.UUCP writes: >"RISC vs. CISC" is, I think, not so much an absolute issue >as an issue of which fits a particular technology better. >When memory speeds are up there with adder speeds, RISC wins. >When adders are much faster than memory, perhaps CISC does. >Different horses for different courses, I think. Every so often someone says something along the lines of "well, implementations of architecture X are faster now, but they require faster memory/<performance measure> than architecture Y. Isn't the Cray-1 still the champ by that measure? Memory delay is 11 clock cycles (93ns @ 8.5ns/cycle), although it is interleaved so non-conflicting accesses can be done concurrently. How many of those cycles do the memory chips have to respond? According to Smith, Weiss, and Pang, in IEEE Trans on Computers, Aug 86, reducing the Cray-1 memory delay to 5 cycles increases the overall performance (on scalar code) by just over 10%. Increasing the delay to 20 cycles (if interleaving and transfering the result back to the cpu alone take 10 cycles, this lets the memory have at least 85ns) hurts (scalar) performance by about 20%, or to "just" 6 MFLOPS. (These numbers also say something about caches on Crays.) -andy ---- UUCP: {arpa gateways, decwrl, uunet, rutgers}!polya.stanford.edu!andy ARPA: andy@polya.stanford.edu (415) 329-1718/723-3088 home/cubicle