[comp.arch] Counterexample to the 50% axiom

mark@mips.COM (Mark G. Johnson) (01/31/88)

{included below}, I measured the die area percentages on the MIPS R2000
CPU, a RISC chip that's been commercially available for more than a year.

If you slice off the top, bottom, left, and right edges of the R2000
chip, eliminating bondpads, drivers, and receivers, 29.3% of the
(remaining) chip area is devoted to the datapath and 32x32 register file.
If you choose to count the R2000's on-chip memory management hardware
(Translation Lookaside Buffer) as "datapath and RAM" then the fraction
rises to 44.8 percent.

So the R2000 seems to be an exception to the adage that
	"If it's less than 50% datapath and RAM, it ain't RISC"


$$$$$$$$$$$$$$$$$ relevant article quotations follow $$$$$$$$$$$$$$$$$$$$

In article <1071@cpocd2.UUCP>, (Howard A. Landman) writes
	> If anyone sees a photo of the chip, here's an easy way to tell
	> RISC from CISC:  Identify the datapath and RAM (including
	> register file and cache).  If they add up to less than half
	> the chip area, it's a CISC.  That's because the rest is probably
	> all control, and any chip that's more than half control does not
	> have a simple architecture.

And in <1094@cpocd2.UUCP>, (Howard A. Landman) says
	> The quick look was not meant to be a scientific definition of
	> RISCness versus CISCness; it's just something I've observed in
	> looking at dozens of chip photos.  As a quick rule of thumb,
	> it's likely to be misleading in some cases, but I've never seen
EMPHASIS--------------------------------------------------^^^^ ^^^^^ ^^^^
	> one yet where it was wrong.  Although the term RISC itself is
EMPHASIS--^^^ ^^^ ^^^^^ ^^ ^^^ ^^^^^
	> almost meaningless these days, it's been abused so often.

After a reply <701@PT.CS.CMU.EDU> came from (Donald Lindsay)
	$ Some recent chips seem to put more real estate into bonding
	$ pads and pin drivers, than into anything else. I assume that
	$ the power consumption is there, too.

the reply-reply <1095@cpocd2.UUCP> from (Howard A. Landman) was
	> As linewidths shrink, pads do not, so they do consume a lot of
	> nanoacreage.  This was so obvious to me that I didn't even
	> think to mention it.  To be accurate, I should have said "the
	> chip core area (excluding pads)", not "the chip area".

-Mark Johnson	*** DISCLAIMER: The opinions above are personal. ***	
UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mark   TEL: 408-720-1700 x208
US mail: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086