jaya@cpsvax.cps.msu.edu (Jayashree Ramanathan) (10/31/89)
I am looking for references that discuss on-chip, off-chip caches. I am interested in the following characteristics: What are the typical sizes as of now ? What is the relative size increase every year due to technology improvements? Placement/replacement policies to manage these caches Is the organization/management of these two caches independent? If not, in what way do they affect each other? Any pointers will be appreciated. Thanks, Jayashree ----------------------------------------------------------------------------- Jayashree Ramanathan E-mail: Graduate Assistant jaya@cpsvax.cps.msu.edu (ARPAnet and CSnet) Dept. of Computer Science jaya@msuegr.BITNET Michigan State University uunet!frith!jaya East Lansing MI48824 -----------------------------------------------------------------------------