mslater@cup.portal.com (Michael Z Slater) (05/17/89)
>Is there any developing consensus concerning second-level cache consistency >protocols in multiprocessor environments for 486 and 68040? E.g. are the >manufacturers such as Intel, Motorola, etc. going to use something like >MOESI in 2nd-level cache chips? Intel has said that they will be introducing a second-level cache controller chip, but they have not given any details. I expect it in early '90. It seems reasonable that they will support something like MOESI, but only time will tell. As for Motorola, they hardly admit anything about the 68040, much less any second-level cache support. I wouldn't hold my breath for second-level support from Moto, since the never did produce any integrated external cache support for the 68020 or 68030, which really could have used it. Michael Slater, Microprocessor Report mslater@cup.portal.com
grunwald@flute.cs.uiuc.edu (Dirk Grunwald) (05/18/89)
What's the MOESI protocol for cache consistency? -- Dirk Grunwald Univ. of Illinois grunwald@flute.cs.uiuc.edu
dkirk@k.gp.cs.cmu.edu (Dave Kirk) (05/18/89)
In article <GRUNWALD.89May17121636@flute.cs.uiuc.edu> grunwald@flute.cs.uiuc.edu (Dirk Grunwald) writes: > >What's the MOESI protocol for cache consistency? >-- >Dirk Grunwald >Univ. of Illinois >grunwald@flute.cs.uiuc.edu The MOESI protocol is the proposed cache consistency scheme to be used with FUTUREBUS. It derives its name from the five states a cache/memory line can assume. If my memory serves me correctly, they were: M: Master O: Owner E: Exclusive (exclusive owner) S: Shared I: Invalid The protocol seems to be closely related to Jim Goodman's Write Once Policy. In fact, I think Jim was involved with the MOESI group. The protocol allows almost any type of device to occupy a position on the Futurebus (i.e. a device with no cache, a device with write-through cache, a device with copy-back cache ...). More information on this can be found in IEEE Futurebus 896.2 document, or there was a paper by Sweazy (i'm going on memory here!) that was published. If anyone needs a full reference just send me email. Dave Kirk kirk@maxwell.ece.cmu.edu --