chris@mimsy.UUCP (Chris Torek) (03/12/88)
>In article <1820@gumby.mips.COM> earl@mips.COM (Earl Killian) writes: >>... The 2x frequency of the clock input is simply a convenience for >>generating two phase CMOS clocking. In article <3356@psuvax1.psu.edu> przemek@gondor.cs.psu.edu (Przemyslaw Klosowski) writes: >... the performance issue is how fast are the signals in the chip running, >and what is on the I/O pins. To be (over)precise: what is the fundamental >frequency in the inside and on the edge of the chip. I know next to nothing about VLSI design, but it is clear that, at least from a theoretical standpoint, two separate clocks running at speed S (even 180 degrees out of phase) and a single clock running at 2S are not the same. Similarly, three clocks at S and one at 3S are `the same' only in that one can be generated from the other. In the limit, an infinite number of clock phases (with the right ones put in the right places at the right times) is equivalent to self-timed logic, not logic running at an infinite number of Hz. I think what przemek@gondor means is that if you fix the chip interface, the 2x clock becomes important. But the interface and the overall architecture are not always that closely bound. It might, for instance, turn out that the MIPS chip could be made to go notably faster by supplying five carefully-tuned phases, but without any other changes. You can almost see the daughterboard lashup in the prototype lab now. . . . -- In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163) Domain: chris@mimsy.umd.edu Path: uunet!mimsy!chris