de@hpcupt1.HP.COM (Dan Epstein) (11/12/87)
Any pointers to articles, or information describing Sun's SPARC chip (used in the SUN-4) would be appreciated! What attributes contributed to the decision of XEROX and AT&T to adopt SPARC over the other available chip-sets? Thanks, Dan Epstein Hewlett-Packard ...hplabs!hpda!de
curry@nsc.nsc.com (Ray Curry) (11/12/87)
In article <6310001@hpcupt1.HP.COM> de@hpcupt1.HP.COM (Dan Epstein) writes: >Any pointers to articles, or information describing Sun's >SPARC chip (used in the SUN-4) would be appreciated! Digital Review, July 13, 1987 has an article on SPARC by Terry Shannon that runs some benchmarks against VaxII/GPX and VAXstation 2000.
rajiv@im4u.UUCP (Rajiv N. Patel) (11/13/87)
I have heard a rumor that SPARC architecture has some essential
features found in the CRISP architecture developed at BELL Labs.
Any comments or similar rumors known to others. I too am really
curious to know about SPARC. Any articles, brochures etc.
Rajiv
NOTE: Please no flames, I make it clear that the above statement is a
rumor I have heard with no confirmations.bcase@apple.UUCP (Brian Case) (11/13/87)
In article <4797@nsc.nsc.com> curry@nsc.UUCP (Ray Curry) writes: >In article <6310001@hpcupt1.HP.COM> de@hpcupt1.HP.COM (Dan Epstein) writes: >>Any pointers to articles, or information describing Sun's >>SPARC chip (used in the SUN-4) would be appreciated! > >Digital Review, July 13, 1987 has an article on SPARC by Terry Shannon >that runs some benchmarks against VaxII/GPX and VAXstation 2000. Also look in Electronics Magazine Sept 3, 1987. You can call Fujitsu at (408) 562-1645. Ask for Kwai. Tell him bcase sent you. He'll be glad to send you manuals and such.
chuck@amdahl.amdahl.com (Charles Simmons) (11/13/87)
In article <2411@im4u.UUCP> rajiv@im4u.UUCP (Rajiv N. Patel) writes: >I have heard a rumor that SPARC architecture has some essential >features found in the CRISP architecture developed at BELL Labs. > >Any comments or similar rumors known to others. I too am really >curious to know about SPARC. Any articles, brochures etc. > >Rajiv I've heard a rumor that the SPARC chip is implemented with rougly 12,000 gates. This seems pretty small, and definitely small enough to attract the attention of AT&T and Xerox. With such a small number of gates, the SPARC chip should be implementable in ECL or GaAs, neh? Hasn't Sun farmed out production of the SPARC chip to some chip maker who will be building an ECL version of the chip? Isn't the chip maker claiming they will get something like 20 or 40 VAX MIPS out of the chip? Wouldn't that excite AT&T and Xerox? -- Cs
bcase@apple.UUCP (Brian Case) (11/13/87)
In article <2411@im4u.UUCP> rajiv@im4u.UUCP (Rajiv N. Patel) writes: >I have heard a rumor that SPARC architecture has some essential >features found in the CRISP architecture developed at BELL Labs. This is not a flame; I am just *extremely* curious to know where people hear such things. So, Rajiv and others, where did you hear this and what did the rumor say? It is true that Dave Ditzel is now at SUN, but he wasn't there during the development of the SPARC. Maybe Dave's presence at SUN is starting these rumors? Just to reiterate, call Kwai at (408) 562-1645 (he works for Fujitsu) and ask him to send you SPARC stuff.
schwartz@gondor.psu.edu (Scott E. Schwartz) (11/14/87)
In article <18203@amdahl.amdahl.com> chuck@amdahl.amdahl.com (Charles Simmons) writes: > With such a small number >of gates, the SPARC chip should be implementable in ECL or GaAs, neh? >Hasn't Sun farmed out production of the SPARC chip to some chip maker >who will be building an ECL version of the chip? I attended a talk this afternoon given by Sun on the Sun4/SPARC. The speaker (Chris Younger) indicated that this is the case. To paraphrase, he said that Sun just designed the chip and they are leaving the construction of it to experts. I'm pretty sure he mentioned ECL as coming soon. -- Scott Schwartz schwartz@gondor.psu.edu
ccplumb@watmath.waterloo.edu (Colin Plumb) (11/14/87)
chuck@amdahl.amdahl.com (Charles Simmons) writes: >I've heard a rumor that the SPARC chip is implemented with rougly >12,000 gates. This seems pretty small, and definitely small enough >to attract the attention of AT&T and Xerox. With such a small number >of gates, the SPARC chip should be implementable in ECL or GaAs, neh? >Hasn't Sun farmed out production of the SPARC chip to some chip maker >who will be building an ECL version of the chip? Isn't the chip maker >claiming they will get something like 20 or 40 VAX MIPS out of the chip? >Wouldn't that excite AT&T and Xerox? I heard 20,000, but either way, it is pretty small. Fujitsu's current implementation is a gate array, but Cypress (sp?) Semiconductor is working on a 20 MHz custom CMOS version, and Bipolar Integrated Technologies is working on a 100 MHz ECL SPARC. How they'll get memory that fast is beyond me, though I heard they were expecting only 50 MIPS instead of the usual 1:1 MIPS:MHz ratio, which points to some wierdness. As far as I know, no one's working on a GaAs version yet, even though Sun talked up the idea. -- -Colin (watmath!ccplumb) Zippy says: Content: 80% POLYESTER, 20% DACRON.. The waitress's UNIFORM sheds TARTAR SAUCE like an 8'' by 10'' GLOSSY..
dennisr@ncr-sd.SanDiego.NCR.COM (Dennis Russell) (11/14/87)
In article <18203@amdahl.amdahl.com> chuck@amdahl.amdahl.com (Charles Simmons) writes: >> With such a small number >>of gates, the SPARC chip should be implementable in ECL or GaAs, neh? >>Hasn't Sun farmed out production of the SPARC chip to some chip maker >>who will be building an ECL version of the chip? > Fujitsu is implementing a gate array version of the SPARC. The part number is MB86900. It runs at 16.67 MHz and is rated at 10 MIPS typ. Cypress Semiconductor is implementing a custom version of SPARC in .8 Micron 2 layer Metal CMOS technology. The part number is CY7C601. It runs at 25 MHz and is rated at 20 Equivalent VAX MIPS. BIT (Bipolar Integrated Technology) is implementing a full custom ECL version of SPARC employing their BIT1 bipolar technology. -- Dennis Russell | NCR Corp., M/S 4720 phone: 619-485-3214 | 16550 W. Bernardo Dr. UUCP: ...{ihnp4|pyramid}!ncr-sd!dennisr | San Diego, CA 92128
mikep@amd.AMD.COM (mike parker) (11/15/87)
In article <1889@ncr-sd.SanDiego.NCR.COM> dennisr@ncr-sd.SanDiego.NCR.COM (0000-Dennis Russell) writes: > >Fujitsu is implementing a gate array version of the SPARC. The part number >is MB86900. It runs at 16.67 MHz and is rated at 10 MIPS typ. > >Cypress Semiconductor is implementing a custom version of SPARC in .8 >Micron 2 layer Metal CMOS technology. The part number is CY7C601. It runs >at 25 MHz and is rated at 20 Equivalent VAX MIPS. > >BIT (Bipolar Integrated Technology) is implementing a full custom ECL >version of SPARC employing their BIT1 bipolar technology. >-- >Dennis Russell | NCR Corp., M/S 4720 Yes, this is the way I had heard it too, but it makes no sense. If they get 10 VAX MIPS at 16.67 then all other things being equal they need 33 MHz to get 20 VAX MIPS. The thing is that all other things are not equal, when you go twice as fast your memory system has to provide instructions twice as fast to maintain MIPS. Even worse, clock to Q on address lines and setup time on data lines don't necessarily get halved when clock rate doubles (because package capacitances don't change). This means that at twice the speed the memory chips have to be more than twice the speed of the ones used at the lower speed. If the memory performance doesn't keep up, then you get pushed from 0 wait states to 1 wait state and performance goes down. So SPARC won't do 20 VAX MIPS until they get to 33 MHZ chips and rams that are more than twice as fast as the ones they use now. Would somebody with a SUN 4 pop it open and tell me what speed SRAMS are used in the 128 Kbyte cache at 16.67 MHz? I am dying to know. mikep disclaimer: I have a vested interest as strategic marketing manager for the Am29000. I'm sure AMD doesn't accept responsibility for my opinions, especially on usenet. -- UUCP: {hplabs,amdcad,ihnp4,allegra}!amd!mikep ARPA: amdcad!amd!mikep@decwrl.dec.com USPS: Mike Parker, AMD, P.O. Box 3843, M.S. 6, Sunnyvale, Ca. 94088 AT&T: 408-982-6772
peter@sugar.UUCP (Peter da Silva) (11/17/87)
I understand that the SPARC can execute 68000 code, in an emulation mode. At least Sun talks about the Sun-4 running Sun-3 stuff at 7 MIPS effective. Would it be possible to use a SPARC as a 68000/68020 accelerator in other computers? No flames, please. I know nothing about the SPARC but what Sun's advertising department has been reported to have said by a third party. -- -- Peter da Silva `-_-' ...!hoptoad!academ!uhnix1!sugar!peter -- Disclaimer: These U aren't mere opinions... these are *values*.
henry@utzoo.UUCP (Henry Spencer) (11/19/87)
> I understand that the SPARC can execute 68000 code, in an emulation mode. At > least Sun talks about the Sun-4 running Sun-3 stuff at 7 MIPS effective... I would guess that they are talking about recompiling it first. There is no 68000 emulation in the SPARC architecture manual (not in the copy I saw, anyway), and I would be awfully surprised to see Sun increase the complexity of the cpu by an order of magnitude just for backward compatibility! Mmm, I suppose it's just conceivable that there's a 68020/68881 pair in some dark corner of the Sun-4 CPU board, but that too would surprise me. If they are not talking about recompilation (or mechanical translation of the binary into a SPARC binary, which might be practical), then it must be software simulation and I'd be skeptical of the MIPS number. You could probably make a 68020 simulator for the SPARC that would run pretty nicely, but 7 MIPS is a lot for that approach. -- Those who do not understand Unix are | Henry Spencer @ U of Toronto Zoology condemned to reinvent it, poorly. | {allegra,ihnp4,decvax,utai}!utzoo!henry
rbl@nitrex.UUCP ( Dr. Robin Lake ) (11/20/87)
In article <1889@ncr-sd.SanDiego.NCR.COM> dennisr@ncr-sd.SanDiego.NCR.COM (0000-Dennis Russell) writes: >In article <18203@amdahl.amdahl.com> chuck@amdahl.amdahl.com (Charles Simmons) writes: >>> With such a small number >>>of gates, the SPARC chip should be implementable in ECL or GaAs, neh? >>>Hasn't Sun farmed out production of the SPARC chip to some chip maker >>>who will be building an ECL version of the chip? >> > >Fujitsu is implementing a gate array version of the SPARC. The part number >is MB86900. It runs at 16.67 MHz and is rated at 10 MIPS typ. Does the SPARC design support cache coordination so that parallel processing is easily supported? Rob Lake BP America R&D -- Rob Lake {decvax,ihnp4!cbosgd}!mandrill!nitrex!rbl