kumarr@ivan.hf.intel.com (Kumar Ranganathan) (11/29/90)
On the 386, a MOV into the SS register causes the next instruction to execute with interrupts disabled. This is to enable ESP to be loaded following the move into SS, so that the stack is consistent before interrupts come in(the LSS instruction does the same thing). Consider the following instruction sequence: MOV SS, stack_seg MOV ESP, stack_ptr Assume paging is enabled and the variables stack_seg and stack_ptr are in different pages. If the reference to stack_ptr generates a page fault, the page fault handler will not be able to get control since interrupts will be disabled. What state will the processor be in under these circumstances ?
johnl@iecc.cambridge.ma.us (John R. Levine) (11/29/90)
In article <1990Nov28.214348.21444@ivan.hf.intel.com> you write: >On the 386, a MOV into the SS register causes the next instruction to >execute with interrupts disabled. ... >[if you load SS and then SP, and the load of SP causes a page fault, >what happens?] Consult the Intel 80386 Programmer's Reference Manual, order number 230985, available from Intel for about $25, probably even less if you work for them. Section 9.8.14.2 addresses this very situation. In general, traps and exceptions switch to a different privilege level or even a different task. Each privilege level in a task has a different stack, so it is no problem that the faulting code has a bogus stack -- nothing is pushed on it. It mentions that if the operating system for some reason takes page faults in the faulting tasks's context, then code in that task should only use the indivisible LSS instruction rather than two moves. See section 6.3.4.1 for an overview of task switching. The 486 Programmer's Reference Manual, order number 240486, contains the same information in sections 9.9.14.2 and 6.5.1. Regards, John Levine, johnl@iecc.cambridge.ma.us, {spdcc|ima|world}!iecc!johnl
ts@cup.portal.com (Tim W Smith) (11/30/90)
Speaking of MOV SS,BLETCH masking interrupts for the next instruction, what happens if the next instruction is also a move into SS? Will interrupts be masked again for the next instruction? What would a long series of MOV SS instructions do to interrupt response? Tim Smith