keith@mips.COM (Keith Garrett) (01/18/90)
In article <6186@celit.fps.com> hutch@fps.com (Jim Hutchison) writes: >So here is a thought I was toying with. How about allowing for library calls >to trap and re-write there calls as the appropriate instruction? the mips architecture includes coprocessor usable bits (one per coprocessor). if the instruction stream includes a coprocessor instruction for a coprocessor that is marked unusable, an exception is taken. The exception handler can then emulate the instruction, or trap, as appropriate. CP0, the system control coprocessor, is always usable in kernel mode, regardless of the state of its usable bit. since the usable bits are under software control, they can be set differently for each process. this allows some user processes to have IO access, while blocking others. it also reduces the context switch time for processes that don't use floating point. when a new process is spawned, its CP1 (floating point coprocessor) usable bit is set to unusable. when a floating point instruction is encountered, it is trapped to the exception handler, the old context is saved from the fp registers, the usable bit is flipped, and the instruction is restarted. keith -- Keith Garrett "This is *MY* opinion, OBVIOUSLY" UUCP: keith@mips.com or {ames,decwrl,prls}!mips!keith USPS: Mips Computer Systems,930 Arques Ave,Sunnyvale,Ca. 94086