eprice@sagpd1.UUCP (Eric Price) (01/06/90)
Howdee Netlanders,
Seems the other morning whilst I was jump starting my self with
a little eXpreSSo, I read a blurb in the buisness section of the
San Diego Union about a new floating point type chipster jointly
developed by Motorola and United Technologies. Said somthin' 'bout
Jillillions of Flops. Still I hav'nt heard 'enny thin' about it.
Anyone out there care to squelch the gossip ... or add more fuel
to the fire.
Pax et Bonum
eric aka eprice@sagpd1phil@motaus.UUCP (Phil Brownfield) (01/10/90)
In article <579@sagpd1.UUCP>, eprice@sagpd1.UUCP (Eric Price) writes: > Seems the other morning whilst I was jump starting my self with > a little eXpreSSo, I read a blurb in the buisness section of the > San Diego Union about a new floating point type chipster jointly > developed by Motorola and United Technologies. Said somthin' 'bout > Jillillions of Flops. Still I hav'nt heard 'enny thin' about it. > Anyone out there care to squelch the gossip ... or add more fuel > to the fire. > I waited a couple of days, hoping someone with more info than I would post. No such luck :-), so here goes: It's a real thing. On January 3, TRW and Motorola announced a new chip called the CPUAX. TRW designed the architecture, which they call "SuperChip". Motorola fabs it now, TRW will later. It has been fabbed, and is functional. It was developed under the DoD's VHSIC program, and will be used by the US Navy in aerospace signal processing applications. Later generations are planned, perhaps for commercial apps. I know next to nothing about the architecture. The implementation is interesting: 0.5 micron CMOS (yes, 0.5), triple layer metal with salicide, 4 million devices, die size 1.59 X 1.49 inches (NOT cm). Sorry, I don't know the clock speed. It's built up of 142 macrocells, of which 61 must be functional for the part to work. A small second chip, the "Universal Processor", operates if a macrocell fails, dynamically reconfiguring the CPUAX and keeping it functional in applications requiring high reliability. 200 SP MFLOPS are claimed. Disclaimers: I am not a spokesman for Motorola or TRW. I had nothing to do with developing the CPUAX. All of the above is extracted from press releases. -- Phil Brownfield, Motorola Semiconductor {cs.utexas.edu!oakhill, mcdchg}!motaus!phil oakhill!motaus!phil@cs.utexas.edu probably works
news@polyslo.CalPoly.EDU (News Guru) (01/10/90)
In article <2413@motaus.UUCP> phil@motaus.UUCP (Phil Brownfield) writes: [stuff deleted] > >I know next to nothing about the architecture. The implementation >is interesting: 0.5 micron CMOS (yes, 0.5), triple layer metal with >salicide, 4 million devices, die size 1.59 X 1.49 inches (NOT cm). >Sorry, I don't know the clock speed. It's built up of 142 macrocells, >of which 61 must be functional for the part to work. A small second >chip, the "Universal Processor", operates if a macrocell fails, >dynamically reconfiguring the CPUAX and keeping it functional in >applications requiring high reliability. 200 SP MFLOPS are claimed. > >Phil Brownfield, Motorola Semiconductor >oakhill!motaus!phil@cs.utexas.edu probably works An article on this appears in EE Times 1/8/90, p.4, "TRW fabs VHSIC superchip." I am somewhat troubled by one sentence in the article. I quote (w/o permission, sorry), "The company achieved 0.5-micron feature sizes on a high numerical-aperture g-line stepper from Nikon." [The "company" being Moto ] Umm, given the recent complaints that the Japanese are taking over the semiconductor processing equipment market ... I'm wondering if the US very-high-speed IC program for the DOD is being built on Japanese technology? Do I have the right Nikon? -Myron // mdeale@cosmos.acs.calpoly.edu
andrew@dtg.nsc.com (Lord Snooty @ The Giant Poisoned Electric Head ) (01/10/90)
<25aa6e06.6de@polyslo.CalPoly.EDU>, news@polyslo.CalPoly.EDU (News Guru) writes: > Umm, given the recent complaints that the Japanese are taking over > the semiconductor processing equipment market ... I'm wondering > if the US very-high-speed IC program for the DOD is being built > on Japanese technology? Do I have the right Nikon? I can't answer this question directly, but recent news shows Perkins-Elmer selling off or some-such. Bottom line I read is that there are no more US companies in this market - the Japanese hold 100%. I don't recall my source (sorry - magazine plethora) but do recall this in the context of a Taiwanese chip vendor complaining that if Japan decided to deny him trade, he'd have nowhere else in the world to go, and was lamenting the lack of US manufacturers of this equipment. This was in the last week or two. -- ........................................................................... Andrew Palfreyman andrew@dtg.nsc.com Albania before April!
hoyme@SRC.Honeywell.COM (Ken Hoyme) (01/11/90)
Regarding the use of non-US e-beam equipment on US Government sponsored VHSIC programs. I was involved in Honeywell's equivalent VHSIC program to develop 0.5 micon devices. We used JEOL e-beam equipment from the outset of our program due to the perceived risk of using Perkin-Elmer's AEBLE-150 system (which was partially developed under VHSIC Phase 3 funding, if I am not mistaken). If my memory serves me correctly, the third contractor, IBM, used an internally developed e-beam machine. Both Honeywell and TRW/Motorola felt pressure to use the Perkin-Elmer machine. (Our customer complained regularily at the program reviews about the use of the JEOL machine). The TRW/Motorola team started using the Perkin-Elmer machine. I am not completely sure of the details, since they are second hand, but they received their machine late, and when it did arrive, it did not meet specs and was not capable of reliably patterning 0.5 micron feature sizes. Much of the lateness in TRW's program can be attributed to the inability to climb the 0.5 micron learning curve when the equipment was incapable of yeilding test circuits. I am not sure whether the AEBLE machine ever met the specs. They ultimately switched to Japanese equipment. The JEOL system was not without it's problems. They were finicky, with many hand-tuned components. Resist problems would cause column contamination which would result in lengthy cleaning processes. We regularily reported up-time percentage and would frequently get months with 0-10% up-time per machine. However, when they were up, they patterned accurately. Regarding the sale of Perkin-Elmer's IC equipment division. As I recall, it was a case where no US company was interested in purchasing that division. Japanese firms expressed interest but the US Government is considering blocking such a sale. I do not believe a deal has been consumated yet. Ken Hoyme Honeywell Systems and Research Center (612)782-7354 3660 Technology Dr., Minneapolis, MN 55418 Internet: hoyme@src.honeywell.com
rpeglar@csinc.UUCP (Rob Peglar x615) (01/11/90)
In article <25aa6e06.6de@polyslo.CalPoly.EDU>, news@polyslo.CalPoly.EDU (News Guru) writes: (stuff deleted) > > An article on this appears in EE Times 1/8/90, p.4, "TRW fabs VHSIC > superchip." I am somewhat troubled by one sentence in the article. > I quote (w/o permission, sorry), "The company achieved 0.5-micron > feature sizes on a high numerical-aperture g-line stepper from Nikon." > [The "company" being Moto ] > > Umm, given the recent complaints that the Japanese are taking over > the semiconductor processing equipment market ... I'm wondering > if the US very-high-speed IC program for the DOD is being built > on Japanese technology? Do I have the right Nikon? Yes, you do. In a recent article in Forbes, it was stated that Nikon was buying up Perkin-Elmer technology for chip fab. Article also had the tone of "ominousness" all over it. Details omitted. Land of the Rising Sun? Your guess. Rob -- Rob Peglar Control Systems, Inc. 2675 Patton Rd., St. Paul MN 55113 ...uunet!csinc!rpeglar 612-631-7800 The posting above does not necessarily represent the policies of my employer.