mac3n@babbage.acc.virginia.edu (Alex Colvin) (08/16/89)
In article <24889@winchester.mips.COM>, mash@mips.COM (John Mashey) writes: > In fact, this leads to an interesting question for the old-timers: > how about more reminiscing of instruction-set-architecture features of the > machines designed in the 50s and 60s, that have essentially > disapeared in those designed in the 70s and 80s...? As Dave Wright noted (yes, Dave, I'm still a grad student) the XED instruction isn't to be found much anymore. It turns out to be particularly useful in the absence of a hardware stack for pushing state. The GE635 just XED'd the interrupt vector. The XED'd instructions were responsible for saving whatever state, wherever they wanted. Voila, programmer implemented stacks, queues, whatever. XED was kind of an artifact of the doubleword instruction fetch of the 635. This became difficult as they went to pipelines and variable-length instructions. I see that fixed-width, register-sized instructions are coming back in fashion. Other than that, execute instructions are handy to execute data without messing with page control bits, etc. Nice for interpreters, particularly threaded. Should also work for register pairs. Write your own macro- sequencer? I've heard of a PDP-8 instruction emulator that simply did a XEC through a table, like a fast switch statement without all the break statements. To tie into another thread of discussion, branches in the branch delay slot of some RISCs appear to work like XECs, fetching one remote instruction before restoring the PC. To start another thread, rumor had it that one of the voyager spacecraft uses an execute-like instruction that swaps the acumulator and the instruction fetch register. This can also be used to generate constants. I read that the spacecraft approaching neptune has 32K RAM. Surely this is an interesting long-lived architecture. Anyone know what it looks like?
mmm@cup.portal.com (Mark Robert Thorson) (08/17/89)
I remember reading in an old AFIPS paper that von Neumann believed computers of the future would all have the SQRT instruction, because of the importance of square root in coordinate geometry.
kleonard@gvlv2.GVL.Unisys.COM (Ken Leonard) (08/18/89)
In article <21353@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes:
* I remember reading in an old AFIPS paper that von Neumann believed computers
* of the future would all have the SQRT instruction, because of the importance
* of square root in coordinate geometry.
There was at least one model/series/family of IBM machines that _DID_HAVE_
hardware square root--the 70x0/STRETCH.
In fact, it was _REAL_HARDWARE_ sqrt, not microcoded nor some funny use of
the divider hardware. The sqrt unit was implemented primarily with tunnel-
diode gates and (at the time) a minimum amount of fastest available
transistors.
The divider hardware, but not the multiplier (I think) also used tunnel-diode
gates and the same kind of transistors. These were, by far, the fastest
transistors in the whole machine, too.
--------
regardz,
Kenhenry@utzoo.uucp (Henry Spencer) (08/19/89)
In article <21353@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes: >I remember reading in an old AFIPS paper that von Neumann believed computers >of the future would all have the SQRT instruction, because of the importance >of square root in coordinate geometry. And somebody was listening. :-) IEEE floating point implementations are required to have a square-root primitive (although it doesn't actually have to be in hardware, as the hardware/software boundary is left to the implementor). As I recall, the observation was that it's not significantly more difficult than division when done in hardware, but is a pain to do accurately in software and is important to many algorithms. -- V7 /bin/mail source: 554 lines.| Henry Spencer at U of Toronto Zoology 1989 X.400 specs: 2200+ pages. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
seanf@sco.COM (Sean Fagan) (08/21/89)
In article <303@gvlv2.GVL.Unisys.COM> kleonard@gvlv2.GVL.Unisys.COM (Ken Leonard) writes: >There was at least one model/series/family of IBM machines that _DID_HAVE_ >hardware square root--the 70x0/STRETCH. >In fact, it was _REAL_HARDWARE_ sqrt, not microcoded nor some funny use of >the divider hardware. The sqrt unit was implemented primarily with tunnel- >diode gates and (at the time) a minimum amount of fastest available >transistors. Cray-2's, at least, have sqrt and 1/sqrt (no divide, of course; but they do have reciporocal [sp?]), all in hardware. God, aka Seymour Cray, doesn't believe in microcode. Then again, he also doesn't believe in virtual memory (yes, it does slow things down; so does having to wait noticeably while one extremely large application gets swapped out so that smaller ones can run). Cray-1's and X-MP's don't have them, I believe; they seemed to be new with the 2. If memory serves me, the little instruction-set summary I got this out of also showed a sqrt table in the functional-unit diagram... -- Sean Eric Fagan | "[Space] is not for the timid." seanf@sco.UUCP | -- Q (John deLancie), "Star Trek: TNG" (408) 458-1422 | Any opinions expressed are my own, not my employers'.