lindsay@gandalf.cs.cmu.edu (Donald Lindsay) (02/15/91)
The Microprocessor Report says that the R4000's onchip cache uses four-transistor memory cells, instead of the 6T cells used by Intel and Motorola. Is some new trick involved? Perhaps the higher clock rates make a difference? Or is MIPS just willing to skate on thinner ice? (I notice that the onchip caches are parity protected.) -- Don D.C.Lindsay .. temporarily at Carnegie Mellon Robotics
gunther@probitas.cs.utas.edu.au (Bernard Gunther) (02/15/91)
In article <11959@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: > >The Microprocessor Report says that the R4000's onchip cache uses >four-transistor memory cells, instead of the 6T cells used by Intel >and Motorola. > >Is some new trick involved? Perhaps the higher clock rates make a >difference? Or is MIPS just willing to skate on thinner ice? (I >notice that the onchip caches are parity protected.) I suspect that with the high density technology they're using, MIPS are able to use high-resistance polysilicon resistors as transistor loads instead of the larger PMOS loads commonly used. Cache cells can then be packed closer, since only four NMOS transistors are used per cell (2 for storage, 2 for gating to bit lines) and a single, continuous p-well can be used for their substrate. This has been common practice in very high density SRAMs for a few years now. The downside is that the cells store less charge and have been shown to have higher soft error rates than PMOS load RAMs. Perhaps this justifies the inclusion of on-chip parity... -- Bernard K. Gunther Internet: gunther@probitas.cs.utas.edu.au Department of Computer Science, University of Tasmania GPO Box 252C, Hobart, Tasmania 7001, AUSTRALIA Tel: (002) 202951
sgolson@pyrite.East.Sun.COM (Steve Golson) (02/16/91)
In article <11959@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: >The Microprocessor Report says that the R4000's onchip cache uses >four-transistor memory cells, instead of the 6T cells used by Intel >and Motorola. Moto uses 4T cells for the 68020 and 68030. Honest-to-gosh 4T cells, with no poly pullups. They require periodic refreshing. Steve Golson -- Trilobyte Systems -- Carlisle MA -- sgolson@east.sun.com (consultant for, but not employed by, Sun Microsystems) "As the people here grow colder, I turn to my computer..." -- Kate Bush
baum@Apple.COM (Allen J. Baum) (02/19/91)
[] >In article <4323@eastapps.East.Sun.COM> sgolson@east.sun.com (Steve Golson) writes: > >Moto uses 4T cells for the 68020 and 68030. Honest-to-gosh 4T cells, with >no poly pullups. They require periodic refreshing. I don't believe that this is the case. I asked Moto about 4T cells for caches (and DRAM cells), and was told that the 680x0 had 6T cells, and the 88200, which uses a different process, has 4T cells with poly loads. There is one microprocessor I'm aware of which uses dynamic RAM internally, and that's an ATT DSP. I looked into it a little (using DRAM, that is), figuring if you could use one or 2 T's you could fit twice as much cache on a chip. The answer seems to be that it would be too slow, and to make it fast you have to make the transistors really big, wiping out the space savings, or you'd have to play enough tricks with the decoding that the noise spikes would wreak havoc on the stored charges and it would be unreliable. There have been a couple of papers about DRAM caches. One suggested a valid bit which was guaranteed to leak away faster than the data. So, if the data was going ad, it would also be marked invalid & wouldn't be used. This is a real LRU scheme, you'll notice! Another paper was published in a Hawaiian conference, but I wasn't able to go (rats) and haven't read the proceedings. Has anyone seen that paper, and can you summarize? Any other pointers to papers on the subject? -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum
david@neutron.amd.com (David Witt) (02/19/91)
In article <49311@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes: | [] | >In article <4323@eastapps.East.Sun.COM> sgolson@east.sun.com (Steve Golson) writes: | > | >Moto uses 4T cells for the 68020 and 68030. Honest-to-gosh 4T cells, with | >no poly pullups. They require periodic refreshing. | | | I don't believe that this is the case. I asked Moto about 4T cells for caches | (and DRAM cells), and was told that the 680x0 had 6T cells, and the 88200, | which uses a different process, has 4T cells with poly loads. I was at Motorola Microprocessor Design when the 68020 was originally designed, so this is what I was aware of at the time. I am sure the 68020 used 4T cells with dynamic refresh, the refresh occuring about once every 256 clocks or so. This was one of the reasons for the 8mhz minimum clock frequency. I believe they decided on the 68030 that this was more trouble than it was worth, especially considering the size of the arrays they were dealing with, and went to 6T Ram cells, which they stayed with when they finished the 68040. The 88200 used a poly-load SRAM process, and as such built it's RAM arrays with a 4T poly. I am not sure what the plans are for their next generation, but I would probably guess they would go with 6T Ram cells similar to the 68040. David Witt -- David Witt 1-(512)-462-5846 Advanced Processor Development Advanced Micro Devices domainLand: david@neutron.AMD.COM Austin, Texas