mark@hubcap.clemson.edu (Mark Smotherman) (05/15/89)
Is there any developing consensus concerning second-level cache consistency protocols in multiprocessor environments for 486 and 68040? E.g. are the manufacturers such as Intel, Motorola, etc. going to use something like MOESI in 2nd-level cache chips? Or, do such protocols vary markedly from system to system even given the same processor and availability of cache controller chips from the processor manufacturer? -- Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634 INTERNET: mark@hubcap.clemson.edu UUCP: gatech!hubcap!mark