abakus@uklirb.UUCP (08/20/87)
We want to describe and simulate the MC6502 at RT-Level. Therefore we need a detailed description of the internal structure of this processor, especially of the instruction decoding part. If You have logic diagrams, netlists, or any useful hints to related literature, please mail it to: A. Wodtko & M. Ryba Kaiserslautern University P.O. Box 3049 D-6750 Kaiserslautern F.R.G. e-mail: abakus%uklirb%unido%mcvax@seismo.uucp Many thanks in advance. Kindest regards A. Wodtko M. Ryba