[comp.arch] PgC 7600

neideck@kaputt.enet.dec.com (Burkhard Neidecker-Lutz) (03/22/91)

I'm typing what I've read in a local computer magazine here in Germany.
The magazine isn't exactly known for overwhelming accuracy, so beware.

Summary: I'm underwhelmed.

Done by small British company called PgC, Ltd. (Yawn). Funded by Clive
Sinclair (Oha !). RISC machine with a couple of onboard systems to make cheap
machine implementation possible. The components:

- Timer (connects to IFU)

- Serial control unit (SCU) connects to IFU and external world

- Instruction Fetch Unit (IFU) connects to ECU and external world

- Execution Control Unit (ECU) connects to a ROM and QCache

- CPU  6ns self clocking design coupled with 160 Byte of 3ns RAM

- Memory Controller (MCU) connects to CPU, QCache and external world.

The ROM can be used to store emulation code for CISC instructions ( I assume
this is similar to what Clipper has). Price abotu 600 Deutsche Mark ( 400 $)

External RAM interface:

Separate Data and Address, 160 MByte/sec. bandwidth. Qcache is 32 instructions
deep. Integrated support for dual-ported SRAMS in MCU, claim that this enables
multiprocessor systems. At last a (buggy) table showing planned routes
into the future:

Name 	When 	Price	Technology	MIPS
PgC7600	1/91	400 $	Bipolar		200
PgC7610	2/92	 40 $	CMOS		 80
PgC7620	1/93	100 $	Bipolar		250
PgC7700	2/93	400 $	CMOS	       1000
PgC7710	4/93	200 $	Bipolar	       2000

If you ask me: Too little, too late, no serious performance, no software.
Forget it.

			Burkhard Neidecker-Lutz, CEC Karlsruhe