mark@mips.COM (Mark G. Johnson) (08/26/88)
(Cross-posted to comp.arch by request):
A fascinating patent abstract recently appeared in the IEEE J.SSC:
Seymour R. Cray, PHASE MODULATED PULSE LOGIC FOR GALLIUM ARSENIDE,
filed August 27, 1984, (patent issued Jan 20, 1987), US patent
number 4,638,188.
It's a logic-design-philosophy, plus a circuit design for a logic
gate to be embodied in (apparently depletion-mode-only) GaAs. *Some*
of its interesting features include
{1} The basic gate type is an AND-OR-INVERT with four 4-input ANDs
(and one 4-input OR).
{2} Gates and signals are single-ended, not differential as in ECL.
{3} The logic gate inherently contains a latch; unlike many other
designs, there is exactly one level of logic gates between latches.
{4} The clock is very fast (around two gate delays per clock period).
"A disadvantage of this system is the requirement for providing
accurate clock signals to each gate, but the advantages of higher
speed, noise immunity, and greater packing density far oughtweigh
that disadvantage".
{5} Data is not encoded as a voltage level. Instead it is encoded
as a *phase* relative to the clock waveform.
_____ _____
CLOCK __/ \_____ CLOCK __/ \_____
_____ __ _____
Q __/ \_____ Q \_____/
logic-1 logic-0
A signal that represents the constant "logic-1" is NOT a dc voltage;
it's a square wave in phase with the clock, and a logic-0 is a
square wave that's out of phase with the clock.
{6} Every signal switches exactly once per clock. This means that
there are no low-frequency components in the power supply noise,
so the supply noise is predictable and easily filtered. [fanatical
attention to power distribution & noise on the supplies has been a
hallmark of Cray machines since the CDC-6600 and perhaps earlier.]
{7} The latches inherent in every gate are dynamic, using capacitors
to temporarily store data (for exactly one phase of the clock).
{8} The switching transistors (depletion mode GaAs FETs) have their
gate electrodes capacitively coupled. This is just another way
of saying that R-C level shifters are used to bias the transistors
near pinchoff where they act as switches rather than as resistors.
{9} The capacitors used for temporary (dynamic) storage are implemented
as reverse-biased Schottky diodes. "... care should be exercised
to maintain the bias on all Schottky diodes used as capacitors ..."
"The capacitor takes up a considerable amount of the available
area of an individual logic cell, for example thirty percent (30%)."
{10} There are six GaAs field effect transistors per gate; three for
the first clock half-period (phase), and three for the second
clock half-period. One of each set of 3 is actually a dual-gate
FET so perhaps it's better to quote (2 x 4 FETs) per logic gate.
--
-- Mark Johnson
MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
...!decwrl!mips!mark (408) 991-0208